资源列表
Chapter4
- MIPS is a reduced instruction set computer (RISC) instruction set architecture (ISA)[1]:A-1[2]:19 developed by MIPS Technologies (formerly MIPS Computer Systems). The early MIPS architectures were 32-bit, with 64-bit versions added later.
fifo
- 每一个时钟（clk_100m）上升沿，判断写请求信号是否为高电平，如果为高电平，那么就将数据线上的数据写入FIFO，然后在下一个时钟上升沿，wrf_use增加1，表示FIFO队列里的数据增加了一个。 细心的朋友可能会发现，其实在这一过程中，读请求信号一直为高电平，仔细分析这两张图片，大概可以得出如下判断： 在每个读时钟的上升沿，首先判断读请求信号是否为高电平，若为高电平，再判断FIFO是否为空，如果不为空，那么在下一个read_clock的上升沿将数据读出(us QuartusII desi
urat接收程序
- uart串口接收程序，实现基于Rs232传输线的数据的接收。(UART serial receiving program to realize data receiving based on Rs232 transmission line.)
verilog串口通信程序
- 串口通信程序，用于fpga的串口收发，并讲解了串口通信原理。(Serial communication program is used to receive and transmit the serial port of FPGA, and the principle of serial communication is explained.)
PCM
- verilog的pcm实现，程序书写规范，值得学习。(The PCM implementation of Verilog, the specification of program writing, is worth learning.)
FT245开发
- FT245开发 VHDL
ezidebug-code
- Ezidebug 支持Xilinx，chipscope 寄存器链插入、数据采集和导出、重建testbench和软件仿真验证(Ezidebug supports Xilinx, chipscope register chain insertion, data acquisition and export, reconstruction of testbench and software simulation verification)
led
- 使用quartusII实现verilog的流水灯编程(Use quartusII to implement verilog - flow lamp programming)
counter10
- vhdl编写的十进制计数器，名字叫count10，已配好引脚(VHDL's decimal counter, named count10, has been matched with a pin)
PHY_forPCIE
- PHY相关的用法，主要用于PCIE结构下的说明(PHY Interface for the PCI ExpressTM Architecture)
i2c_verilog
- i2c master controller
消抖模块源代码
- 对fpga中的按键，防摔等部分进行消除抖动(To eliminate the jitter of the key in the FPGA, the fall prevention and other parts)