资源列表
mimasuo
- 数字密码锁 sjtu 用于教学 basys2板子-digital codelock for SJTU
uart
- 串口通信控制器的Verilog实现。包含4个模块：顶层模块、波特率发生器模块、发送模块和接收模块-The serial communication controller Verilog. Contains four modules: the top-level module, the baud rate generator module, transmitting module and receiver module
DDC
- 数字下变频的FPGA实现方法，十分容易理解，初学者很容易掌握，很好的学习资料-Digital down conversion FPGA implementation method is very easy to understand, beginners can easily master
minus
- 无符号数减法，结果在按下输出键后输出，有清零功能-minus no signal can be clear
VGA_pll
- 基于FPGA VGA 时钟的设计,关于pll的设计，可以参考一下-The PLL of vga use in FPGA
jieshoufasong
- 实现FPGA和PC机之间的通信。PC机发送的数据可以通过FPGA显示在数码管上；FPGA通过按键发送的数据可以显示在PC机的串口调试助手上。-Communication between the FPGA and the PC. PC sends the data can be displayed through the FPGA digital tube FPGA through the button to send the data can be displayed on a PC seri
mouse
- Mouse using vhdl language
wehu
- This is an important notes on system verilog from testbench.in
rtl.tar
- This RTL of Router by uisng verilog-This is RTL of Router by uisng verilog
smg
- 对某一引脚高电平计时并用三位数码管显示程序，每秒钟更新一次，quartus ii开发环境，verilog语言编程-Timing in response to a pin of the high level duration with three digital tube display .Quartus_II software development environment and Verilog language preparation
Verilog-HDL-PPT
- Verilog HDL 经典教程夏宇闻老师主讲PPT-The Verilog HDL Classic teach Chengxia Yu Wen speaker teachers PPT
dds_mul
- 简单的多周期dds的verilog编程，出来一个正弦波，可任意改变频率字-Simple multi-cycle dds verilog programming, out of a sine wave, the frequency can be arbitrarily changed words