资源列表
E7_3
- 对基于符号LMS算法的自适应均衡器进行仿真。要求分别进行算法的性能仿真、生成FPGA测试用的输入信号、仿真权值在运算过程中的数据范围(The adaptive equalizer based on the symbol LMS algorithm is simulated. The performance simulation of the algorithm is required, the input signal for FPGA test is generated, and the da
PID_Verilog
- PID算法用verilog语言实现，实测可用，由三个模块组成(The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.)
基于verilog的CAN总线代码
- 用Verilog实现CAN总线，经过仿真验证，可以直接用！
Verilog数字VLSI设计教程（源码）
- Verilog 数字VLSI 设计教程 官方Lab(Verilog Digital VLSI Design Course Official Lab)
ad5764Verilog
- AD5764配置程序 ，使用verilog编写，希望能够帮助大家(AD5764 configuration program, written in verilog, I hope to help everyone)
Verilog HDL
- 2015年全国电子设计大赛F题，时间间隔测量模块，占空比测量模块，ISE编写的verilog程序。(2015 national electronic design competition F title, time interval measurement module, verilog program written by ISE.)
VHDLcounter
- VHDL，四位counter，用Vivado写的，可运行，可模拟，可仿真，可写入硬件里，四个指示灯会每一秒闪一次。
test
- 用fpga实现抢答器功能，包含源程序，可以直接运行。(FPGA is used to implement the function of answering machine, including the source program, which can run directly.)
24_Timer
- 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
Cortex-M1
- Verilog Cortex-M1 source code
VERILOG
- 基础的几个verilog代码实现，讲到case和task的使用。(basic verilog,use case and task ,very usual, i want some help to achieve the design of delta and sigma fractional_n divider.)
package_control-master
- 从github下载的，能够参考设计AXI4的协议接口(AXI4 Verilog template)