资源列表
xilinx_flow
- Xilinx Flow Power point Presentation
FPGA_Architecture
- FPGA Architecture Power point presentation
digitaldesign_Part3
- Digital design course material Part 3/4
The_Verilog_PLI_Handbook
- PLI提供verilog模擬上介於軟體和硬體描述語言的溝通工具-The PLI provides a means for both hardware designers and software engineers to interface their own programs to commercial Verilog simulators.
ethernet_controller_Verilog
- 以太网控制器源码，verilog语言,包含MAC、MII接口-Ethernet controller ,include MAC and MII interfaces ,by verilog
qts_qii55002
- ALTERA on chip fifo. this document is from altera. good resouce
cangyongEDAgjzn
- 4.1 Altera MAX+plusⅡ操作指南 4.1.1 MAX+plusⅡ10.2的安装 4.1.2 MAX+plusⅡ开发系统设计入门 4.2 Xilinx ISE Series的使用 4.2.1 ISE的安装 4.2.2 ISE工程设计流程 4.2.3 VHDL设计操作指南 4.2.4 ISE综合使用实例 4.3 Lattice ispDesignEXPERT的使用 4.3.1 ispDesignEXPERT的安装 4.3.2 原理图输入方式设计
hongsejufengII
- Altera公司的FPGA开发器件，红色飓风II代PCB器件库.DDB。对学习FPGA的同学有帮助。-Altera，FPGA
EWBtutorial
- 电子电路仿真软件EWB的使用手册，介绍软件基本操作与电路仿真。-EWB electronic circuit simulation software, user manual, describes the basic operation and circuit simulation software.
verilog_cordic.tar
- 用verilog实现cordic算法。支持多模，有vecter和rotate模式。支持多种输出-Algorithm to achieve cordic with verilog. Multi-mode, there vecter and rotate mode. Support for multiple output
mealy_machine
- mealy_machine该代码为序列脉冲检测器当输入信号110时电路输出为1否则为0-mealy_machine the code sequence when the input signal pulse detector circuit 110 output is 1 0 otherwise
FPGA-Training_Performance_Time_Memory
- FPGA培训：性能+时间=存储器。提高FPGA系统设计能力的很好的文档，作者提出串行的概念巧妙的达到目标、节省了成本，很值得学习。-FPGA Training: Performance+ Time = Memory. FPGA system design capabilities to improve well documented, the authors propose the concept of smart serial to achieve objectives, cost savin