资源列表
Alu-with-seven-segmetn-output
- This contains VHDL source code for a simple arithmetic logic unit. the input and results are displayed on a 4 digit 7 segment display. The user controls the input throug the use of switches. This design was created for the nexys 2 fpga but can be eas
FPGA_sram
- FPGA向SRAM中写入数据，VHDL编程 -FPGA to SRAM write data, VHDL programming
tPad_VIP
- altera VIP的使用例子,使用SOPC-altera VIP use examle for tpad
verilog
- Verilog进阶学习，Verilog进阶程序学习提高。-The Verilog advanced learning, learning to improve the Verilog Advanced program.
sed1565_nokia7110
- Datasheet for nokia 7110 LCD display
booth
- booth multiplier in verilog
div
- restoring divider in verilog
QPSK_fpga
- QPSK调制和解调的FPGA实现，包括伪码生成等模块-QPSK modulation and demodulation of the FPGA, including the pseudo-code generation modules
microFibo
- Fibonacci Series on Spartan d3
traffic
- 交通灯实验 用PLC实验台调试 成功 交通灯-traffic light
8051
- 8051系列cpu用verilog编写的。-Verilog the compilation American standard encryption algorithm 8051 cpu hardware realizes contains the complete code and the test order.
FPGA-FIR
- 基于FPGA的FIR滤波器设计方法的研究-Based on the FPGA FIR filter design method