资源列表
Design-Of-DDR-SDRAM-Using-Verilog-HDL
- implementation of ddrsdram
Nios
- 基于Nios多核驾驶疲劳检测系统设计FPGA疲劳检测-fatigue detection system design based on Nios multicore
TIMEQUEST-PLL
- 在TIMEQUEST约束PLL输出方法 FPGA-PLL output method FPGA TIMEQUEST constraints
EDAshipinchuli
- 采用FPGA芯片对，CCD摄像头的输出的模拟视频信号进行采集，转换为640*480分辨率的视频数据，并暂存于外部SRAM或SDRAM中-The FPGA chip, the output of the CCD camera analog video signal acquisition, converted to 640* 480 resolution video data, and temporarily stored in the external SRAM or SDRAM
240128
- 240128驱动，验证已通过，驱动芯片6963的12864-240128 device
12864
- 12864的verilog驱动，硬件编码，已经验证通过-12864 device
crc_8
- 基于verilog的并行crc8的校验，已经仿真过，符合设计要求，可以拿去参考-Verilog a parallel crc8 checksum, already simulation, meet the design requirements, you can take reference
scramble
- 在quartusII上已经验证过，很有用的并行加扰程序，用的语言为verilog，需要的可以拿去-Has already been verified in quartusII useful parallel scrambling procedure, the language used for Verilog, need to take look at
piso10
- 很有用的10bit并串转换程序，在quartus上已验证过，需要的可以拿去-10bit and useful string conversion process has been verified in quartus need to take to use with
ser_to_parr
- 很有用的10bit串并转换verilog程序，需要的可以拿去参考下，在quartusII上已验证过-Useful 10bit string and convert verilog program, need to take a reference, has been verified in quartusII
frame_cap
- GPON中下行帧捕捉模块的verilog程序，在quartuaII上已经验证过，需要的可以拿去参考下-GPON downstream frame capture verilog program has already been verified in quartua can take to refer to the following
how-to-write-state-machine
- FPGA状态机设计中的问题，怎样写好三段式状态机，对于FPGA设计者很好的资料-FPGA state machine design issues, how to write a three-state machine, very good information for FPGA designers