资源列表
mux16_1
- 高速并行，有符号16选一的MUX，完整的VERILOG功能模块和测试平台-High-speed parallel, 16 elections have signed one MUX, a complete functional module and test platform VERILOG
fpga_report
- “以FPGA为核心的系统设计” FPGA讲座，主要讲了FPGA的主要应用场合，主要结合国赛中的应用。-" The FPGA design as the core of the" FPGA talks mainly about the main applications of the FPGA, the main race with the application of the country.
hdmitx
- hdmi tx solution is from company that can help hdmi design using fpga
sr8
- 8bit移位暫存器 隨著CLK觸發 每次將資料依序輸入暫存器 且為FIFO-8bit shift register with the CLK input is triggered each time the data register and the FIFO order
VerilogCode_7_segment_decoder
- Verilog Code for seven segment decoder for the code to be implemented on Altera DE2 board
VerilogCode_8-bit_2to1_mux
- Verilog Code for 8 to 1 multiplexer for the code to be implemented on Altera DE2 board
VerilogCode_BCD_counter
- Verilog Code for a BCD counter and it is implemented on Altera DE2 board-Verilog Code for a BCD counter and it is implemented on Altera DE2 board
vga1
- VGA 接口模块，800*600接口时序verilog实现-VGA interface module, 800* 600 interface timing verilog implementation
3des_vhdl_latest
- 3DES的VHDL IP核，64位 标准FIPS 46-3 NIST,并且使用3组64位密钥-The VHDL implementation 3DES，The core complies with the Triple-DES 64-bit block cipher defined in FIPS 46-3 NIST standard and operates with three 64-bit keys. Functional Descr
digital-tube
- 实现开发板上的数码管静态循环显示0~F。通过这个实验，掌握采用Verilog HDL语言编程实现7段数码管显示译码器的方法。-The digital realization of the development board cycling static display 0 ~ F. Through this experiment, using Verilog HDL language to master programming 7-segment display decoder method
SynplifyPro_Quartus_v5_v4_1
- Quartus仿真软件SynplifyPro应用指导-Guidance on the application simulation software SynplifyPro Quartus
xcs30xl
- Xilinx Spartan-XL data book