资源列表
freq
- 在Quartus下VHDL编写的一个频率测试模块，自动转换为十进制数字输出到数码管上。-A frequency test modules written in VHDL in Quartus under are automatically converted to the decimal number is output to the digital tube.
FIFO
- Quartus下VHDL编写的一个FIFO模块，调试于c6000系列。控制Cache输入输出数据-A FIFO module in VHDL Quartus, commissioning c6000 series
AD
- 在Quartus环境下，VHDL语言的一个AD转换程序，即128k采样速率的模数转换-Quartus environment, the VHDL language, one of the AD conversion, 128k sampling rate analog to digital conversion
counter
- 在Quartus环境下verilog语言编写的一个4位加数器，选择的是一位位进位，是学习时序的好例子-Quartus environment verilog language of a four addend, the choice is a binary, is a good example to learn the timing
Seven_vote
- 在Quartus环境下verilog编写的一个7位投票器，拥有主持人的控制端口-Quartus environment Verilog prepared a seven vote, with the host control port
uartverilog
- FPGA与上位机通过串口调试助手进行串口通信，回发传过来的数据-FPGA and host computer through the serial port debugging assistant serial communication, and pass over the data postback
TASK51_DE0
- FPGA内嵌51核，已通过调试及下载验证。-FPGA embedded 51-core, debug and download validation.
89S52-control-DDS
- 使用89S52单片机控制AD9854 DDS板产生正弦信号，单片机接口采用5V转3.3V元件74LVC4245-89S52 microcontroller control of AD9854 DDS board to produce a sinusoidal signal, the microcontroller interface, 5V to 3.3V components 74LVC4245
eetop.cn_tcd1209
- TCD1209D 时序驱动采用VHDL语言-TCD1209 drive
ds18b20_seg7
- 基于 FPGA+ds18b20 温度计 设计 一ds18b20接受 数据 以数码管 显示温度-Designed based on FPGA+ Ds18b20 thermometer ds18b20 accept the data to the digital display temperature
My_RASrm
- 流水线处理器的Verilog代码，结构简单，基本功能-the pipeline processor，code in Verilog
vhdl-clock-with-vga-output-for-Nexys-2
- Vhdl code for a working digital clock which can be displayed on a vga screen. The clock can be set using a single pushbutton. This project was written for nexys 2 board but can be easily ported to any other fpga using vhdl.