资源列表
TimingConstraint
- xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material
fir_liujiao
- 利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter
FrqDiv
- VerilogHDL语言编写的分频编序，在FPGA上调试通过-VerilogHDL language compilation of sub-frequency sequence, the FPGA debugging through
Xilinx_TMR_XVRWARE_Library
- XVRWARE Library Xilinx Inc. The XVRWARE Synthesis library provides macros and synthesis examples for constructing TMR circuits in VHDL for the Virtex architecture
crc32
- crc循环冗余校验码，用于对传输信号进行编码校验，是信息更可靠-crc cyclic redundancy check code used to transmit coded signals to verify, the information is more reliable
2fsk
- 对信号实现2FSK调制,2FSK就是用数字信号去调制载波的频率（移频键控），是信息传输中使用得较早的一种调制方式。它的主要优点是：实现起来较容易；抗噪声与抗衰减的性能较好；在中低速数据传输中得到广泛的应用。-the performance of 2FSK based on verilog
VerilogHDLcourse
- Verilog数字系统设计教程，作者夏宇闻电子书籍-Verilog digital system design tutorials, e-books by XIA Yu-Wen
waveform_gen_latest.tar
- 波形发生器，用于编写testbentch文件。非常实用-Waveform generator, for the preparation of testbentch files. Useful
fpuvhdl_latest.tar
- 浮点数运算的FPGA实现，包括仿真文件。-FPGA realization of floating-point operations, including the simulation file
vhld_tb_latest.tar
- vhdl testbentch 编写模板。非常实用-vhdl testbentch prepared templates. Useful
cf_fir_latest.tar
- It is a fir to implement in a FPGA. It s not desenvolved for me it is a good work of another person
Avalon_VGA
- vga显示彩色图像ip，alter开发板-vga display color image,vhdl,quartus