资源列表
UART
- LM3S系列微处理器异步总线通信例程，有5个-LM3S series asynchronous microprocessor bus communication routines, there are five
verilog
- verilog实现的数字频率计8位数码管输出显示同时矩形波分档输出-verilog implementation of digital frequency meter
fsk
- FSK的编码 运用VHDL实现代码仿真-FSK encoding
FSK-VHDL
- FSK调制与解调VHDL程序及仿真，仿真通过-FSK modulation and demodulation process, and VHDL simulation, simulation by
VHDLprogram
- VHDL的程序包，包括LED控制，LCD控制、DAC0832接口电路、URAT、FSK\PSK\MASK调制、波形发生器等。适合工程参考-VHDL package, including the LED control, LCD control, DAC0832 Interface Circuit, URAT, FSK \ PSK \ MASK modulation, such as waveform generator. Reference for the project
ad
- STC12C5A60S2的AD转换，并送入LCD显示-STC12C5A60S2 the AD converter, and into the LCD display
FDWT
- it explains the ID DWT concepts. and the codes are in VHDL and MATLAB
AES256-XILINX10.1
- 用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计，采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware descr iption language implementation of the AES-256 encryption algorit
IP
- ALTERAL的stratix4的IP核的使用讲解PPT，便于理解Stratix的IP核调用-The IP core stratix4 ALTERAL the use to explain the PPT, to facilitate the understanding the Stratix of IP core call
pcirw
- quartusII环境下实现FPGA与PCI9054通信。根据PCI9054规范控制lhold、lholda、ads、blast、lbe、lwr等握手信号的时序，可完成上位机通过PCI总线读写FPGA本地地址空间的功能- Communication between FPGA and PCI9054 in QuartusII IDE.Implementation for the timing of handshake signals such as lhold, lholda, ads,bla
LUdecompose
- 基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档-LU decompose based on verilog
HDB3
- 基于FPGA的HDB3编码器和译码器的实现源代码-the decoder and encoder based on FPGA