资源列表
EPM240_analog_lcd_moudle_controller(sch_pcb_democo
- EPM240做的模拟屏控制器，有原理图（PDF）,PCB(PDF),手册（DOC）,程序（verilog），PIN文件。淘宝上有得买-EPM240 analog LCD moudle controller with schematic，PCB,demo code，handbook，pin assiment file。
ALU_ise10migration
- It s vhdl source code for 32 bit ALU.
dds2_ok
- 利用LPM_ROM和HDL设计的一个DDS信号发生器，分辨率优于1HZ，ROM表长度8位，8位频率控制字。-HDL design using LPM_ROM and a DDS signal generator, the resolution is better than 1HZ, ROM table length 8 bits, 8-bit frequency control word.
Uart_Send
- UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.
clock
- verilog 实现的跑表程序。可以对这个程序加以修改，可是显现电子钟的设计。设计可以根据需要实现分秒。同时可以改成是LED的跑等程序。功能强大的很！-verilog implementation stopwatch program. This procedure can be modified, but the show clock designs. Design can be according to the need to achieve every second. At the same
eMMC-CardStandard
- eMMC 多媒体卡协议标准完整版。网上无法找到，再次独家发布。-eMMC multimedia card protocol standard full version. Alone this one.
一位半加器
- 这是一个用vhdl语言设计的一位半加器以及一位全加器的代码，经过QUARTUS验证可以运行！
twice_clk
- 对输入时钟进行2倍频 已在modelsim中通过仿真 建议进行后仿 应用上来看 是可以使用的-the function of the module is frequency multiplication，and the module had been test and verified by modelsim,so the products can be employed with 100 ease by each consumer.think you!!!!
ADPCMverilog
- ADPCM编码的Verilog编码实现，代码有详细的注释，编译通过-ADPCM coding Verilog code, the code has detailed notes, compiled by
VerilogHDL
- 用Verilog HDL语言编写的跑马灯小程序，可直接在FPGA上运行-With the Verilog HDL language of the Marquee applet can be run directly on the FPGA
ADV7180
- files describe how to configure an ADV7180
tranreceive
- 基于fpga的串口通信，好东西，希望大家喜欢-Fpga-based serial communication, a good thing, hope you like