资源列表
cyclone_ivProgramming-Guide
- 本应用笔记提供了一组简单易用的指南和一列在Cyclone® IV 设计中需要考虑的因素。 Altera 建议在设计过程中遵循本应用笔记中介绍的指南-This application note provides a set of simple and easy to use guidelines and a list of needs to be considered in the Cyclone IV design factors. Altera is recommended t
half_band
- 半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考-Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference
CLK_div
- 用verilog写的分频器，包括16分频，8分频，4分频，2分频等，代码简单，效率高，个人感觉很实用且对初学者很有帮助-Written in verilog divider, including 16 points frequency, frequency eight points, 4 points frequency, frequency division 2, etc., the code is simple, high efficiency, personal feeling is ve
CIC
- 很好的级联积分梳妆CIC滤波器verilog 源代码，希望对大家有所帮助-Good cascade integral dressing CIC filter source code, hope to be of help for you
S_FIFO
- 自己编写的同步Verilog FiFO 还是不错的 可以-Verilog 同步 FIFO
A_FIFO
- 自己编写的Verilog 异步fifo 有一定的个参考价值 -Verilog 异步 Fifo
ps_to_sp
- 自己琢磨的 Verilog 并行数据 转串行数据 串行数据转并行数据 有一定的个参考意义 -Verilog PS_to_SP
ALU
- 自己编写的Verilog ALU 效果还不错 可以-Verilog ALU
cuce(ok)
- 在起始信号与停止信号之间计数，而且通过仿真验证成功-Between the start signal and stop signal counts, and success is validated by computer simulation
Ycbcr444-to-Ycbcr422-example
- Ycbcr444 转 Ycbcr422 的源码-the Verilog code of Ycbcr444 to Ycbcr422 example
chuanbing-and-bingchuan
- 基于FPGA的通信，实现串并并串转换，简单容易理解，代码完整，希望对你们有帮助-FPGA-based communication, and achieve string and string conversion, simple and easy to understand, code integrity, and I hope you have help
fftshixian
- 基于FPGA编写的verilog代码，在xilinx上仿真实现FFT变换-FPGA-based verilog code written in xilinx FFT transform Simulation