资源列表
rtl_viterbi_veeRen
- RTL design Viterbi decoder using VHDL
SPI_verilog_veeRen
- serial peripheral interface using tx and rx
Viterbi_algorithm_VeeRen
- Viterbi algorithm using Verilog
viterbi_decode_veeren
- Viterbi decoding algorithm
SPI_veeren
- Serial peripheral interface using verilog
LP-LFSR
- LPLFSR for Low power test pattern generation_V
lfsr_top
- LP LFSR for low power test pattern generation_V
ASCII_PACKAGE
- ASCI package in VHDL for verilog implementation
binbcd8
- Binary to BCD conversion in VHDL for implementation in FPGA
microprogramming
- this program for demonstration how work is a FIR filter with microprogramming control
JTAG-control
- this program for demonstration how work is finite control the jtag
FIR-filter
- this program for demonstration how work is a FIR filter