资源列表
Ch9
- 《Verilog HDL数字系统设计及仿真》第九章常见功能电路的HDL模型源代码-" Verilog HDL design and simulation of digital systems," Chapter IX common functional circuits HDL model source code
Ch8
- 《Verilog HDL数字系统设计及仿真》第八章有限状态机的设计源代码-" Verilog HDL design and simulation of digital systems." Chapter VIII of the finite state machine design source code
Ch7
- 《Verilog HDL数字系统设计及仿真》第七章可综合模型设计源代码-" Verilog HDL design and simulation of digital systems," Chapter VII of the source code can be integrated model design
Ch6
- 《Verilog HDL数字系统设计及仿真》第六章Verilog HDL测试模块源代码-" Verilog HDL design and simulation of digital systems," Chapter VI test module Verilog HDL source code
Ch5
- 《Verilog HDL数字系统设计及仿真》第五章任务、函数与编译指令源代码-" Verilog HDL design and simulation of digital systems," Chapter V tasks, functions and compiler directives
Ch4
- 《Verilog HDL数字系统设计及仿真》第四章 Verilog HDL行为级建模源代码-" Verilog HDL design and simulation of digital systems," Chapter IV behavioral modeling Verilog HDL source code
Ch3
- 《Verilog HDL数字系统设计及仿真》第三章源代码-Verilog HDL
vhdl
- 8bit latch and a led code
ML_CTL
- CPLD、FPGA控制8×8点阵显示流水效果-FPGA control dot matrix display water effects.
src
- FPGA数数码管控制程序，外部接口简单，给出各段数码管的字符即可。-Number FPGA digital control program, the external interface is simple, the characters are given to each segment digital tube.
4_BUZZER_PWM
- FPGA通过PWM波控制蜂鸣器产出不同的音调。-FPGA wave PWM control buzzer output by different tones.
PS2
- 原创！FPGA通过PS2键盘输入，在数码管显示输入。-Original! FPGA via PS2 keyboard input, the digital display inputs.