资源列表
C5G_AD_DA_hsmc
- 关于altera最新的C5代的开发板的DA、AD转换资料-The latest generation C5 on altera development board DA, AD conversion data
key_board
- 刚刚调试好的，好用的fpga接收ps2键盘程序-A nice fpga receive ps2 keyboard program
flash_keymux
- M25P40系列flash的读写代码，包含按键组合功能，便于仿真调试-M25P40 flash
zynq_IP
- 这是德致伦公司培训 zynq 7000系列的一个经典例子，是关于自定义挂载核的VGA接口-this is a example for ZYNQ 7000
Elham-Zahraei-Salehi_-Sina-Saharkhiz-(1)
- here it is a file which is consist of design of a MIPS pipeline in verilog, it also has test part an it work perfectly. the code is written in good way to understand it easily
music_ic
- 此為VHDL之音樂IC設計，透過Max Plus II將設計結果顯示。-This is the music of IC design VHDL, designed by Max Plus II results will be displayed.
Lab5
- 此為VHDL之非同步觸發、清除之單擊電路與同步觸發、清除之單擊電路設計-This is a non-synchronous triggering of VHDL, click to clear the circuit and synchronization trigger, click to clear the circuit design
Lab4
- 此為VHDL之同步清除電路與非同步清除電路之模擬與電路設計-This is a synchronous clear circuit VHDL synchronize with non-clear analog circuits and circuit design of
Lab1~3
- 此為VHDL之暫存器、栓鎖器、三態匣、計數與除頻電路以及時脈產生電路-This is a register of VHDL, Latch, tri-state box, count divider circuit and clock generator circuit
FIX_ONE_ROW_ROM
- 此為文字型LCD顯示液晶透過矩陣與狀態機顯示內容-This is a text-based LCD display through matrix liquid crystal display with a state machine
e_piano
- 自己编写的电子钢琴的源码，大家可以下载并且试试，很好用的-I have written an electronic piano source, you can download and try, good use
regfor24
- 这是一个24小时时钟，整体使用verilogHDL编写，六位数码管显示，分为三个模块，分别为扫频模块，计时显示模块，和顶层模块-it s a clock for 24 hours .use verilogHDL to write the project ,it s easy to understand.