资源列表
nios
- sample program for up3 education kit
quanjiaqi
- 使用verilog HDL实现全加器的功能-Use verilog HDL to achieve full adder function
uart_fpga1110
- 自己实现了一个简易的无校验UART协议。altera EP4C6E验证-Own implements a simple no parity UART protocol. altera EP4C6E verification
cymometer
- 硬件频率计的实现，包括十分频，门控信号产生，频率测量等-cymometer implementation， involving 10 times divider, generating gate controling signal and frequency measurement
shizhong
- 这个程序是基于Quartus II的，能通过数码管显示时、分、秒，具有闹钟的功能，能通过按键校时。-his program is based on the Quartus II, and when through digital display hours, minutes, seconds, and has an alarm clock function, button through school.
usb
- usb数据采集实验，用ft245作为usb芯片用-use usb to send data to computer
DE2_70_LTM
- VERILOG语言环境的LTM显示开发封装模块。-VERILOG language environment of the LTM display development encapsulated module.
LCD1602
- 基于altera cyclone 的EP2Q208C8 FPGA的1602液晶显示模块，其中包括驱动模块和测试模块，驱动模块可以作为通用模块，给其他文件调用-Altera cyclone display module is based on the 1602 LCD EP2Q208C8 FPGA, including drive module and test module, drive module can be used as general-purpose modules to other
buzzer
- 基于EP2Q208C8,用Verilog编写的蜂鸣器音乐发生器，蜂鸣器能够根据开关的选择对应地弹奏曲子-Based EP2Q208C8, written using Verilog buzzer music generator, buzzer able to play the song based on the corresponding selection switch
lcd
- fpga开发板实现lcd1602显示屏显示数字时钟。开发板测试通过-FPGA development board to achieve LCD1602 display digital clock. Through the development board test
jisuanqi
- fpga开发板实现按键两位数加减乘除运算。通过数码管显示-FPGA development board to achieve key two digit add, subtract, multiply and divide operations. Through the digital tube display
SandGlass
- VHDL源代码，用的是quartus9.0，显示的是电子沙漏-VHDL, displaying the sandglass