资源列表
shiyan
- 使用FPGA设计的一种跑表，但只是用来实验上的仿真-FPGA design using a stopwatch, but only for simulation on
divider
- 使用模为2N+1的计数器,让输出时钟在X-1(X在0到2N-1之间)和2N时各翻转一次,则可得到奇数分频器,但是占空比并不是50 -The use of modulo 2N+1 counter, let the output clock in the X-1 (X between 0 and 2N-1) and 2N of the turning once, then can get the odd divider, but the duty ratio is not 50
grantyz
- 4倍频鉴相功能模块，利用Verilog hdl语言编写的-4x phase function module using Verilog hdl language
cordic_base_j
- This code implement a interation in cordic pipelline
adder
- This code implement add between 2 number
addsub
- This code implement add or sub between 2 number
rrc
- This code implement rrc filter
acc
- This code has function to accumulate
endat
- endat 2.2 接口内核，发送命令至编码器或从编码器接收位置值-endat 2.2 interface cores, sending commands to the encoder or received the encoder position values
complexadder
- 32位复数加法器，利用ISE里的float IP核-32 complex adder, using the ISE in the float IP core
complexMul
- 复数乘法器，利用ISE里的float IP核，实现了32位复数的乘法-Complex multiplier, using the ISE in the float IP core to achieve the 32 complex multiplications
butterfly
- FFT模块里的蝶形运算单元，需要用到加法器，减法器，二选一选择器-FFT module of butterflies, need to use an adder, a subtracter, a second election selector