资源列表
State-machine-design-techniques
- 状态机设计-英文-如何编写状态机-case-State machine design techniques for Verilog and VHDL
PWM
- 基于Avalon总线的PWM的实现，verlog语言编程-PWM-based Avalon bus implementations, verlog language programming
counter
- 基于Xilinix公司的BASYS2板子完成的一个计数器电路以及仿真代码。-Based on a counter circuit board Xilinix company BASYS2 completed and simulation code.
FullAdder
- full adder verilog de2-70
DieuKhienLed
- dieu khien led DE2-70
Decoder
- decoder 3 to 8 verilog
FSM
- lap trinh FSM may trang thai
Counter1s
- counter number one to nine after 1s-counter number one to nine after 1s
barrelshifter
- Here is barrel shifter source code with verilog language
paralleladder
- This a verilog source code for parallel adder-This is a verilog source code for parallel adder
uart
- 通过CPLD，可以进行和电脑的串口通讯。-By CPLD, and computers can be serial communication.
part1
- LAB 1 - Part 1 DE0 VHDL Tutorial