资源列表
PS2_Kbd
- Communicate peripheral PS2 keyboard using VHDL
DongHo
- design a clock using KIT DE1
PS2_Final
- nios ii with ps2 keyboard
ldpc_encoder_10bit
- LDPC Encoder 10-Bit Parity Check
risc32_datapath
- Risc - 32 Bit Datapath Only
risc64
- Risc 64 - Bit Verilog Code
spi_verilog
- 开发语言Verilog,实现spi总线控制，内部有顶层文件，仿真文件等。-Development language Verilog, realize spi bus control, internal top-level file, simulation files.
verilog-LCD1602-DS18B20
- 基于FPGA的温控风扇，带DS18B20，LCD1602-FPGA-based temperature control fan with DS18B20, LCD1602
hash_function_sha3
- The synthesis software is Xilinx ISE version 14.4. The low throughput core has been synthesized targeting a very cheap Spartan 3 (XC3S5000-4FG900). This project is licensed under the Apache License, version 2. I prefered on the internet
verilog_sdram
- I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to
fir128
- Discrete-Time FIR Filter, Filter length - 128, Number of Multipliers - 8, Number of States - 8.
FX2LP-FPGA
- xilinx FPGA XC6LX9 与CY7C68013通信程序-xilinx FPGA XC6LX9 and communication program CY7C68013