资源列表
UartLoop
- xilinx FPGA XC6LX9 串口通信程序 返回发送内容-xilinx FPGA XC6LX9 serial communication program returns to send content
jkff_behav.v
- This is JK-FF in Behavioural Style.
divby3.v
- This Divider by 3.-This is Divider by 3.
lfsrupdwn.v
- This left shift register.-This is left shift register.
divby4.5.v
- This Divider by 4.5.-This is Divider by 4.5.
MVLSI_CBP_16.-FPGA-based-for-Implementation-of-Mu
- Paper on FPGA-based-for-Implementation-of-Multi-Serials-to-Ethernet-Gateway
IIC
- 硬件语言verilog实现IIC控制器，严格按照IIC协议编写硬件控制器行为及代码-Hardware language verilog realize IIC controllers, written in strict accordance with IIC protocol hardware controller behavior and codeHardware language verilog realize IIC controllers, written in strict acco
IO-timing-constrain-in-fpga
- 对FPGA的IO口的时序分析小结，能够详细理解其约束时序规则-FPGA timing analysis summary of IO port, capable of a detailed understanding of its timing constraint rules
huffman
- 用verilog硬件语言实现了动态huffman编码，能够压缩字符串文件，展示了硬件的压缩率-Using verilog hardware descr iption language to achieve a dynamic huffman coding to compress the string file, showing the hardware compression rate
VGA
- vga显示硬件模块verilog语言编写，实现了一个动画显示，适合于初学者学习。-vga display hardware module verilog language to achieve an animated display, suitable for beginners to learn.
fft
- fft in verilog code for fpga
internal_reset.v
- code for internal reset in fpga