资源列表
DDS
- 可以产生正弦波，三角波、锯齿波、方波，要求频率1Hz-100kHz，步进1Hz，具有自动扫频功能； 正弦波的相位可调，方波的占空比可调； -Can generate sine wave, triangle wave, sawtooth wave and square wave, the required frequency of 1 hz- 100 KHZ, step 1 hz, with functions of automatic frequency sweep The pha
verilog-source-codes
- the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
how_to_create_nios_II_application
- Nios II basic development tutorial project
Program
- 用ALTERA公司的FPGA写的网卡W5300程序-W5300 in fpga
M130095EC
- vhdl code for uart. data tx from pc to fpga nd vice versa
LPM_ROM
- 该程序是一个正弦信号发生器，信号的频率可控，利用FPGA的ROM，可以对正弦信号的相应电位进行查表，具体电位的地址由计数器得到。-The program is a sinusoidal signal generator, the frequency of the signal controlled by the FPGA ROM, may be a sinusoidal signal corresponding to the potential of the table, the address
CNT4_S
- 该程序为运用VHDL语言，基于FPGA平台实现的一个四进制的计数器。-The program for the use of VHDL language, FPGA-based platforms to achieve a quaternary counter.
f_adder
- 利用VHDL的语言，实现考虑进位的全加器，该程序带中的加法器带有使能端，可以更好地实现所需功能。-Using VHDL language to achieve considering the carry bit full adder, the program with the adder with Enable, can better achieve the desired function.
M-series-digital-signal
- 第一路用于产生一个10Mbps的M序列，第二路产生10Kbps到100Kbps的M序列，数据率可以按10Kbps步进。-The first way to generate a sequence of M 10Mbps, the second way to produce 10Kbps to 100Kbps M-sequence data rate can 10Kbps steps.
ADS1252
- 内容为运用FPGA驱动ADS1252的工程文件，时钟频率为10M,内部使用了锁相环，可以自行调节采样频率。-FPGA-driven content for use ADS1252 project file, the clock frequency is 10M, internal use of the phase-locked loop, you can adjust their own sampling frequency.
PCI9054_Interface
- PCI9054接口控制逻辑,带有DMA功能和普通寄存器功能-PCI9054 Interface
lcd5110-frequency
- 用nakio 5110显示波形的Verilog程序！主要学习液晶的Verilog驱动！-Program with nakio 5110 Verilog waveform display! The main study of Verilog LCD driver!