资源列表
traffic
- traffic light control by FPGA Quartos
CAN_VHD.ZIP
- CAN VHDL Controller Area Network en languge VHDL CAN VHDL Opencore
HSDI-communcation-interface-IP
- 基于FPGA的HSDI接口的程序，调试可用。-FPGA-based programs HSDI interfaces, debug available.
SPDIF-interface-IP-core
- SPDIF数字音频接口的的程序，已写成通用IP核形式。-The program SPDIF digital audio interface has been written in the form of common IP core.
UART-IP-based-on-queue
- 基于队列传输的UART的IP核程序，已调试可直接使用。-Queue-based transmission of UART IP core procedures have been debugging can be used directly.
grey-code--FIFO-IP-core
- 基于格雷码的FIFO的IP核，调试可用于通信接口的队列传输。-Gray code based on FIFO IP core, debugging can be used for communication queue transmission interface.
SPI_slave-SPI-control-ADS8364
- FPGA控制ADS8364采集，采集的数据通过SPI上传，SPI做从机slave。-FPGA control ADS8364 acquisition, upload the data collected through the SPI port, SPI do slave slave.
FPGA source files
- this is an introduction to best source code
sdram_ov7670_vga
- 基于OV7670摄像头的FPGA采集工程,通过VGA显示输出。-OV7670 camera based on FPGA acquisition projects through VGA display output.
PCIe_Lab(ALTERA-V5PCIe)
- 这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。 -Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.
low_level_decrypt_8
- This folder consists of five vhdl files. These are low level entities of top level entity named decrypt_8 project. -This folder consists of five vhdl files. These are low level entities of top level entity named decrypt_8 project.
decrypt_8
- This file is top level entity of decrypt_8 project. This project is 8_bit decryption for TEA algorithm. You can change number of bits (at least 32 bit for TEA). This project is only for one round. You should use input as encryption output so that you