资源列表
Project10
- Hamming codes can detect up to two-bit errors or correct one-bit errors without detection of uncorrected errors. By contrast, the simple parity code cannot correct errors, and can detect only an odd number of bits in error. Hamming codes are perfect
quanjia
- 一位全加器 一位全加器 -A full adder a full adder a full adder a full adder
include_c_to_verilog
- catapult c函数库，可以进行fpga定点仿真，非常有价值。-catapult c library
cbf
- catapult c 常规波束形成程序，已转化为verilog语言，并且完成modelsim验证-catapult c beamforming program
ADSample3
- 这是我自己做的项目中的FPGA程序，和之前的是一个项目中一个-This is my own project FPGA program, and before a project
testcordic
- catapult c cordic程序，可以转换成verilog语言，完成用modelsim进行仿真，结果可以与matlab进行比较。-catapult c cordic program
mylu
- catapult c任意维矩阵求逆程序，已完成verilog语言转换验证。-catapult c matrix inverse program。
code
- c++语言转verilog语言，程序员不需要学习verilog即可对fpga原型进行快速仿真，本例为catapult c语言的fft程序，可以利用catapult转换工具转成verilog语言， 用modelsim进行仿真，并且可以加各种约束。-c++ program translate verilog program。
24chdetcpld
- CPLD 24个通道循环检测有时序可控制反馈回路时间差-24-channel detector has a feedback loop to control the timing
driver_board_VerilogHDL
- CPLD 8移位控制测试通过边沿检测信号-CPLD 8 shift control signal edge detection test
booth-mutiplier
- booth乘法器的verilog实现及仿真。 内含verilog源码和modelisim仿真源码，清晰的实现了硬件乘法器，代码注释清晰-booth multiplier verilog verilog implementation and simulation contains the source code and modelisim simulation code, clear notes
ADC_Sample
- 本人自己经过实践检验的ADC数据采集程序，通过FPGA采集数据，并用SRAM做缓存，用Verilog编写的，非常好用。-I own proven ADC data collection procedures, data collection through the FPGA and SRAM do with caching, using Verilog prepared, very easy to use.