资源列表
VGA
- 在分辨率为800 * 600的VGA显示器的行和场各显示一个边长为100的正方形方块移动。 -In a resolution of 800* 600 VGA display of line and field shows a side length is 100 square square of mobile.
yibufifo
- 讲诉fifo配置设计中，一些程序例程，仅供参考，相互学习一下-Recounts fifo configuration design, some routine, for reference, to learn about each other
B2BCD
- 基于VHDL的二进制转BCD码，简单高效，占用资源少，是国外一本最新书籍提倡的一种写法。-Binary switch based on VHDL BCD code, a simple and efficient method of resource usage, less is foreign advocates a kind of writing a new book.
monitoringV5
- 文件的FPGA是基于Xilinx ISE写的，所用开发板为zedboard7020 484系列，完成的功能为：读取XADC里的温度，VCC，并存储到RAM中，通过流水灯实现翻看，读取等功能.-Document is based on Xilinx ISE FPGA wrote, the use of development board for zedboard7020 484 series, completed functions: reading XADC in temperature, VC
AD
- 控制AD7934的信号verilog,控制AD7934的信号verilog-control the ad7934
sd-card-experiment
- it`s a project for MSP430, use it by IAR can do some projection about SD card-it`s a project for MSP430, use it by IAR can do some projection about SD card
detect_3
- 任意3比特序列数据检测,只要输入任意3比特的数据序列，检测到之后，使输出置高为一。-Detection of any sequence data of 3 bits, as long as the input data sequence of three arbitrary bits, after the detection, the output is set high one.
include
- c++转verilog，快速进行fpga原型验证，不需要学习verilog，只需要学习c++即可，已经成功应用于某实时系统设计。-c++ translate verilog
CLOCK
- 用VHDL语言实现时钟功能，可进行分和秒设置-Clock function using VHDL, can be set up in minutes and seconds
adders
- half,full,4,8,10 and 12bit RCA adders
Verilog
- verilog程序合集，里面包含众多小程序，对于verilog的学习很有帮助。-verilog Collection, which contains a number of small procedures, verilog helpful.
textfilereading2
- It is a VHDL code for the operation of file reading by IEEE commands which can transfer the multiplr data