./
./spislave/
./spislave/tags/
./spislave/branches/
./spislave/trunk/
./spislave/trunk/spislave/
./spislave/trunk/spislave/sw/
./spislave/trunk/spislave/bench/
./spislave/trunk/spislave/bench/Makefile
./spislave/trunk/spislave/bench/tb_spigpio.v
./spislave/trunk/spislave/doc/
./spislave/trunk/spislave/doc/src/
./spislave/trunk/spislave/doc/FPGA1.dia
./spislave/trunk/spislave/doc/FPGA1.jpeg
./spislave/trunk/spislave/rtl/
./spislave/trunk/spislave/rtl/verilog/
./spislave/trunk/spislave/rtl/verilog/spigpio.v
./spislave/trunk/spislave/rtl/verilog/lgpl-3.0.txt
./spislave/trunk/spislave/rtl/vhdl/
./spislave/trunk/spislave/backend/
./spislave/trunk/spislave/backend/zilogic/
./spislave/trunk/spislave/sim/
./spislave/trunk/spislave/sim/gate_sim/
./spislave/trunk/spislave/sim/gate_sim/src/
./spislave/trunk/spislave/sim/gate_sim/out/
./spislave/trunk/spislave/sim/gate_sim/run/
./spislave/trunk/spislave/sim/gate_sim/log/
./spislave/trunk/spislave/sim/gate_sim/bin/
./spislave/trunk/spislave/sim/rtl_sim/
./spislave/trunk/spislave/sim/rtl_sim/src/
./spislave/trunk/spislave/sim/rtl_sim/out/
./spislave/trunk/spislave/sim/rtl_sim/run/
./spislave/trunk/spislave/sim/rtl_sim/log/
./spislave/trunk/spislave/sim/rtl_sim/bin/
./spislave/trunk/spislave/syn/
./spislave/trunk/spislave/syn/zilogic/
./spislave/trunk/spislave/syn/zilogic/src/
./spislave/trunk/spislave/syn/zilogic/out/
./spislave/trunk/spislave/syn/zilogic/run/
./spislave/trunk/spislave/syn/zilogic/log/
./spislave/trunk/spislave/syn/zilogic/bin/