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文件名称:FPGA_exp

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    12.22mb
  • 已下载：
    0次
  • 提 供 者：
    张***
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

一个开发板培训项目的所有Verilog程序例子

其中包括 led 分频 M4kram Rom 等程序-Verilog examples
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.(0).cnf.cdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.(0).cnf.hdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.asm.qmsg
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.cbx.xml
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.cmp.cdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.cmp.hdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.cmp.kpt
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.cmp.logdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.cmp.rdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.cmp.tdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.cmp0.ddb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.db_info
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.eco.cdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.fit.qmsg
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.hier_info
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.hif
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.lpc.html
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.lpc.rdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.lpc.txt
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.map.cdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.map.hdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.map.logdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.map.qmsg
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.pre_map.cdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.pre_map.hdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.rtlv.hdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.rtlv_sg.cdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.rtlv_sg_swap.cdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.sgdiff.cdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.sgdiff.hdb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.sld_design_entry.sci
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.sld_design_entry_dsc.sci
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.syn_hier_info
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.tan.qmsg
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson.tis_db_list.ddb
FPGA_exp/例程/ex1/ex1/ledverilog/db/johnson_global_asgn_op.abo
FPGA_exp/例程/ex1/ex1/ledverilog/db/prev_cmp_johnson.asm.qmsg
FPGA_exp/例程/ex1/ex1/ledverilog/db/prev_cmp_johnson.fit.qmsg
FPGA_exp/例程/ex1/ex1/ledverilog/db/prev_cmp_johnson.map.qmsg
FPGA_exp/例程/ex1/ex1/ledverilog/db/prev_cmp_johnson.qmsg
FPGA_exp/例程/ex1/ex1/ledverilog/db/prev_cmp_johnson.tan.qmsg
FPGA_exp/例程/ex1/ex1/ledverilog/incremental_db/compiled_partitions/johnson.root_partition.map.kpt
FPGA_exp/例程/ex1/ex1/ledverilog/incremental_db/README
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.asm.rpt
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.cdf
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.done
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.dpf
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.fit.rpt
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.fit.smsg
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.fit.summary
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.flow.rpt
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.map.rpt
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.map.summary
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.pin
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.pof
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.qpf
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.qsf
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.qws
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.sof
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.tan.rpt
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.tan.summary
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.v
FPGA_exp/例程/ex1/ex1/ledverilog/johnson.v.bak
FPGA_exp/例程/ex1/ex1/ledverilog/johnson_assignment_defaults.qdf
FPGA_exp/例程/ex1/ex1/Thumbs.db
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/prev_cmp_seg7.asm.qmsg
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/prev_cmp_seg7.eda.qmsg
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/prev_cmp_seg7.fit.qmsg
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/prev_cmp_seg7.map.qmsg
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/prev_cmp_seg7.qmsg
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/prev_cmp_seg7.sta.qmsg
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/prev_cmp_seg7.tan.qmsg
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.(0).cnf.cdb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.(0).cnf.hdb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.asm.qmsg
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.cbx.xml
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.cmp.bpm
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.cmp.cdb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.cmp.ecobp
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.cmp.hdb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.cmp.kpt
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.cmp.logdb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.cmp.rdb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.cmp0.ddb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.cmp_merge.kpt
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.db_info
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.eco.cdb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.eda.qmsg
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.fit.qmsg
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.hier_info
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.hif
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.lpc.html
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.lpc.rdb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.lpc.txt
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.map.bpm
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.map.cdb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.map.ecobp
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.map.hdb
FPGA_exp/例程/ex2/ex2/seg7_verilog/db/seg7.map.kpt
FPGA_exp/例程/ex2/

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