sim/testbench/tb.v
sim/testbench/clk_rst_gen.v
sim/testbench/glbl.v
sim/cic.do
sim/work/_info
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sim/work/clk_rst_gen/verilog.asm
sim/work/clk_rst_gen/_primary.dat
sim/work/tb/_primary.vhd
sim/work/tb/verilog.asm
sim/work/tb/_primary.dat
sim/work/dpram_block/_primary.vhd
sim/work/dpram_block/verilog.asm
sim/work/dpram_block/_primary.dat
sim/work/shift_reg_module/_primary.vhd
sim/work/shift_reg_module/verilog.asm
sim/work/shift_reg_module/_primary.dat
sim/work/glbl/_primary.vhd
sim/work/glbl/verilog.asm
sim/work/glbl/_primary.dat
sim/qq.mpf
sim/qq.cr.mti
用blockram实现移位寄存器.doc
src/shift_reg_module.v
src/dpram_block.v
sim/work/_temp
sim/work/clk_rst_gen
sim/work/tb
sim/work/dpram_block
sim/work/shift_reg_module
sim/work/glbl
sim/testbench
sim/work
sim
src