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文件名称:jianxiang

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    20.12mb
  • 已下载：
    0次
  • 提 供 者：
    aaaa****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于ISE的鉴频、鉴相器，开发板：xilinx公司spartan 3E 500.精确度1hz,1度。完全正确。-Based on ISE' s Kam-frequency phase detector, development board: xilinx company spartan 3E 500. Precision 1hz, 1 degree. Entirely correct.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

jianxiang/mymodel/model/bitgen.xmsgs
jianxiang/mymodel/model/ChipS_1.cdc
jianxiang/mymodel/model/clk7seg.vhd
jianxiang/mymodel/model/clk7seg_wrapper.ngc
jianxiang/mymodel/model/clock_generator_0_wrapper.ngc
jianxiang/mymodel/model/device_usage_statistics.html
jianxiang/mymodel/model/dlmb_cntlr_wrapper.ngc
jianxiang/mymodel/model/dlmb_wrapper.ngc
jianxiang/mymodel/model/edkBmmFile.bmm
jianxiang/mymodel/model/edkBmmFile_bd.bmm
jianxiang/mymodel/model/ilmb_cntlr_wrapper.ngc
jianxiang/mymodel/model/ilmb_wrapper.ngc
jianxiang/mymodel/model/in_first_wrapper.ngc
jianxiang/mymodel/model/in_second_wrapper.ngc
jianxiang/mymodel/model/in_third_wrapper.ngc
jianxiang/mymodel/model/jiping.v
jianxiang/mymodel/model/jiping.vhd
jianxiang/mymodel/model/leds_8bit_wrapper.ngc
jianxiang/mymodel/model/lmb_bram_wrapper.ngc
jianxiang/mymodel/model/map.xmsgs
jianxiang/mymodel/model/mb_plb_wrapper.ngc
jianxiang/mymodel/model/mdm_0_wrapper.ngc
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtSvgBLKD_Dimensions.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtSvgDiag_Colors.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtSvgDiag_Globals.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtSvgDiag_StyleDefs.css
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtTinySvgBLKD_BusLaneSpaces.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtTinySvgBLKD_Busses.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtTinySvgBLKD_Functions.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtTinySvgBLKD_Globals.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtTinySvgBLKD_IOPorts.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtTinySvgBLKD_Main.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtTinySvgBLKD_Peripherals.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtTinySvgBLKD_Processors.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtTinySvgBLKD_StyleDefs.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtTinySvgDiag_BifShapes.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtXdsGen_Colors.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtXdsGen_Globals.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtXdsGen_HTMLDatasheet.css
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtXdsGen_HTMLIPSection.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/microblaze_w_blkd.xml
jianxiang/mymodel/model/microblaze/blockdiagram/.dswkshop/svg10.dtd
jianxiang/mymodel/model/microblaze/blockdiagram/microblaze.css
jianxiang/mymodel/model/microblaze/blockdiagram/microblaze.svg
jianxiang/mymodel/model/microblaze/blockdiagram/svg10.dtd
jianxiang/mymodel/model/microblaze/clock_generator_0.log
jianxiang/mymodel/model/microblaze/data/microblaze.ucf
jianxiang/mymodel/model/microblaze/etc/bitgen.ut
jianxiang/mymodel/model/microblaze/etc/bitgen.ut.virtex5
jianxiang/mymodel/model/microblaze/etc/download.cmd
jianxiang/mymodel/model/microblaze/etc/fast_runtime.opt
jianxiang/mymodel/model/microblaze/etc/fast_runtime.opt.virtex5
jianxiang/mymodel/model/microblaze/hdl/clk7seg_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/clock_generator_0_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/dlmb_cntlr_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/dlmb_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd
jianxiang/mymodel/model/microblaze/hdl/ilmb_cntlr_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/ilmb_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/in_first_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/in_second_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/in_third_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/leds_8bit_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/lmb_bram_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/mb_plb_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/mdm_0_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/microblaze.vhd
jianxiang/mymodel/model/microblaze/hdl/microblaze_0_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/microblaze_stub.vhd
jianxiang/mymodel/model/microblaze/hdl/micron_ram_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/out_first_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/out_second_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/out_third_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/proc_sys_reset_0_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/push_buttons_4bit_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/rs232_port_wrapper.vhd
jianxiang/mymodel/model/microblaze/hdl/switches_8bit_wrapper.vhd
jianxiang/mymodel/model/microblaze/implementation/cache/cache.cat
jianxiang/mymodel/model/microblaze/implementa

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