Designs/alu/
Designs/alu/alu.prj
Designs/alu/alu.v
Designs/alu/testbench.v
Designs/array_mult/
Designs/array_mult/array_mult.prj
Designs/array_mult/array_mult.v
Designs/array_mult/array_mult_vhdl.prj
Designs/array_mult/coregen.prj
Designs/array_mult/fulladd.prj
Designs/array_mult/fulladd.v
Designs/array_mult/fulladd_vhdl.prj
Designs/array_mult/lastrow.prj
Designs/array_mult/lastrow.v
Designs/array_mult/lastrow_vhdl.prj
Designs/array_mult/multcell.prj
Designs/array_mult/multcell.v
Designs/array_mult/multcell_vhdl.prj
Designs/array_mult/multrow.prj
Designs/array_mult/multrow.v
Designs/array_mult/multrow_vhdl.prj
Designs/array_mult/testbench.v
Designs/carryskip/
Designs/carryskip/carryskip.prj
Designs/carryskip/carryskip.v
Designs/carryskip/carryskip_vhdl.prj
Designs/carryskip/fulladd.v
Designs/carryskip/fulladd_p.prj
Designs/carryskip/fulladd_p_vhdl.prj
Designs/carryskip/nbitfulladd.v
Designs/carryskip/testbench.v
Designs/cla/
Designs/cla/carry_block.prj
Designs/cla/carry_block.v
Designs/cla/carry_block_vhdl.prj
Designs/cla/carry_lookahead.v
Designs/cla/carry_lookahead_adder.prj
Designs/cla/carry_lookahead_adder_vhdl.prj
Designs/cla/cla.prj
Designs/cla/cla_vhdl.prj
Designs/cla/coregen.prj
Designs/cla/fulladd.v
Designs/cla/testbench.v
Designs/dsp/
Designs/dsp/alu.v
Designs/dsp/dsp.prj
Designs/dsp/dsp.v
Designs/dsp/dsp_vhdl.prj
Designs/dsp/ex.prj
Designs/dsp/ex.v
Designs/dsp/ex_vhdl.prj
Designs/dsp/reg.v
Designs/ex6_2/
Designs/ex6_2/ctrl.v
Designs/ex6_2/ctrl_vhdl.prj
Designs/ex6_2/dp.prj
Designs/ex6_2/dp.v
Designs/ex6_2/dp_vhdl.prj
Designs/ex6_2/mult.prj
Designs/ex6_2/mult.v
Designs/ex6_2/mult_vhdl.prj
Designs/ex6_2/sys.prj
Designs/ex6_2/sys.v
Designs/ex6_2/sys_vhdl.prj
Designs/ex6_2/testbench.v
Designs/nbitfulladd/
Designs/nbitfulladd/coregen.prj
Designs/nbitfulladd/fulladd.prj
Designs/nbitfulladd/fulladd.v
Designs/nbitfulladd/fulladd_vhdl.prj
Designs/nbitfulladd/nbitfulladd.prj
Designs/nbitfulladd/nbitfulladd.v
Designs/nbitfulladd/nbitfulladd_vhdl.prj
Designs/nbitfulladd/testbench.v
Designs/parity/
Designs/parity/coregen.prj
Designs/parity/parity.prj
Designs/parity/parity.v
Designs/parity/parity_vhdl.prj
Designs/parity/testbench.v
Designs/sec5_3_3/
Designs/sec5_3_3/mod.prj
Designs/sec5_3_3/mod.v
Designs/shifter/
Designs/shifter/coregen.prj
Designs/shifter/shifter.prj
Designs/shifter/shifter.v
Designs/shifter/shifter_vhdl.prj
Designs/shifter/testbench.v
Designs/tlc/
Designs/tlc/coregen.prj
Designs/tlc/sequencer_vhdl.prj
Designs/tlc/timer.prj
Designs/tlc/timer_vhdl.prj
Designs/tlc/tlc.prj
Designs/tlc/tlc.v
Designs/tlc/tlc_ctrl.v
Designs/tlc/tlc_sta.v
Designs/tlc/tlc_testbench.v
Designs/tlc/tlc_timer.v
Designs/tlc/tlc_vhdl.prj