实验目的

1．学习一般有限状态机的设计；

2．实现串行序列的设计。

二、设计要求

1．　　先设计0111010011011010序列信号发生器；

2．　　再设计一个序列信号检测器，若系统检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。

-Purpose of the experiment 1. Learning the general design of finite state machine　2. Serial sequence design. Second, the design requirements 1. Sequence of the first signal generator design 0111010011011010　2. And then design a sequence of signal detection, if the system detects the serial sequence of 11 010 output is " 1" , otherwise the output is " 0" , and its simulation and hardware testing.