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文件名称:an497_design_example

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.51mb
  • 已下载：
    0次
  • 提 供 者：
    Sil***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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修正介绍说明

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LCD driver VHDL example
(系统自动生成,下载前可以参看下载内容)

下载文件列表

LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/code/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/code/lcd_controller.v
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_controller.cr.mti
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_controller.mpf
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_controller.v
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/lcd_testbench.v
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/transcript
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/vsim.wlf
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/wave.bmp
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/wave.do
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/@u@f@m2_altufm_parallel_bmm/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/divider/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/fsm/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_controller/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/verilog.psm
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/_primary.dat
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/lcd_testbench/_primary.vhd
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/modelsim/work/_info
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(0).cnf.cdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(0).cnf.hdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(1).cnf.cdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(1).cnf.hdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(2).cnf.cdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(2).cnf.hdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(3).cnf.cdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(3).cnf.hdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(4).cnf.cdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(4).cnf.hdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(5).cnf.cdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.(5).cnf.hdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.asm.qmsg
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.asm_labs.ddb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.cbx.xml
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.cmp.cdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.cmp.hdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.cmp.logdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.cmp.rdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.cmp.tdb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.cmp0.ddb
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.dbp
LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler/quartus/db/lcd_controller.db_info
LCD_Controller_Altera_MAX_II_C

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