文件名称:LIP3001CORE_cpu
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- 上传时间:2012-11-16
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文件大小:159.47kb
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CPU Verilog Module source code
(系统自动生成,下载前可以参看下载内容)
下载文件列表
project_2_impl_1/project_2_impl_1.psi
project_2_temp_1/analysis.args1.file
project_2_temp_1/hdlAnalyze_sysverilogfile
project_2_temp_1/hdlAnalyze_verilogfile
project_2_temp_1/precision.log
project_2_temp_1/precision_rtl.sdc
project_2_temp_1/project_2_impl_1.psi
project_2_temp_1/sys_con_rep.sdc
project_2_temp_1/sys_fsm.rep
project_2_temp_1/sys_rtl.ixdb
project_2_temp_1/unfolded_blocks.txt
project_2_temp_1/rtlc_libs/work/.vextid.map
project_2_temp_1/rtlc_libs/work/2ext0.pkg
project_2_temp_1/rtlc_libs/work/2ext1.pkg
project_2_temp_1/rtlc_libs/work/cheetah_tmp_file
project_2_temp_1/rtlc_libs/work/clk_gate.mod
project_2_temp_1/rtlc_libs/work/clk_gate.mod.body
project_2_temp_1/rtlc_libs/work/main_bus.int
project_2_temp_1/rtlc_libs/work/main_bus.int.body
project_2_temp_1/rtlc_libs/work/rtlc_version_info
project_2_temp_1/rtlc.out/.rtlc_compile
project_2_temp_1/rtlc.out/.top
project_2_temp_1/rtlc.out/autotop.conf
project_2_temp_1/rtlc.out/legalmodmap.db
project_2_temp_1/rtlc.out/rtlc.args
project_2_temp_1/rtlc.out/rtlc_args1.file
project_2_temp_1/rtlc.out/vmw.mem_contents
project_2_temp_1/rtlc.out/INCR/emptymod.list
project_2_temp_1/rtlc.out/INCR/hier.list
project_2_temp_1/rtlc.out/INCR/incr_driver.log
project_2_temp_1/rtlc.out/INCR/incr_rtlc.log
project_2_temp_1/rtlc.out/FSM_REPORT/clk_gate.rpt
project_2_temp_1/rtlc.out/FSM_REPORT/sys.rpt
src/cpu.v
src/datapath.v
src/decode.v
src/defines.v
src/lib_fpga.v
src/mem.v
src/memory_board.v
src/mult.v
src/pio.v
src/register.v
src/rom.v
src/sasc_brg.v
src/sasc_fifo4.v
src/sasc_top.v
src/sys.v
src/test.v
src/timescale.v
src/top.v
src/uart.v
src/vdec_dsp16_decode.v
src/vdec_dsp16_regfile.v
src_sv/cpu.sv
src_sv/datapath.sv
src_sv/datapath.v
src_sv/decode.v
src_sv/defines.v
src_sv/lib_fpga.v
src_sv/main_bus.sv
src_sv/mem.v
src_sv/memory_board.sv
src_sv/mult.v
src_sv/pio.sv
src_sv/register.v
src_sv/sasc_brg.v
src_sv/sasc_fifo4.v
src_sv/sasc_top.v
src_sv/sys.sv
src_sv/timescale.v
src_sv/top.sv
src_sv/uart.sv
.jaguarc
precision.log
project_2.psp
setup_datapath.tcl
setup_sys.tcl
setup_top.tcl
project_2_temp_1/rtlc.out/INCR/tmp
project_2_temp_1/rtlc.out/INCR/AREA
project_2_temp_1/rtlc_libs/work
project_2_temp_1/rtlc.out/NM
project_2_temp_1/rtlc.out/NET
project_2_temp_1/rtlc.out/MEM
project_2_temp_1/rtlc.out/INCR
project_2_temp_1/rtlc.out/FSM_REPORT
project_2_temp_1/rtlc.out/EXEM_MACRO_DIR
project_2_temp_1/rtlc.out/depend
project_2_temp_1/rtlc_libs
project_2_temp_1/rtlc.out
project_2_impl_1
project_2_temp_1
src
src_sv
project_2_temp_1/analysis.args1.file
project_2_temp_1/hdlAnalyze_sysverilogfile
project_2_temp_1/hdlAnalyze_verilogfile
project_2_temp_1/precision.log
project_2_temp_1/precision_rtl.sdc
project_2_temp_1/project_2_impl_1.psi
project_2_temp_1/sys_con_rep.sdc
project_2_temp_1/sys_fsm.rep
project_2_temp_1/sys_rtl.ixdb
project_2_temp_1/unfolded_blocks.txt
project_2_temp_1/rtlc_libs/work/.vextid.map
project_2_temp_1/rtlc_libs/work/2ext0.pkg
project_2_temp_1/rtlc_libs/work/2ext1.pkg
project_2_temp_1/rtlc_libs/work/cheetah_tmp_file
project_2_temp_1/rtlc_libs/work/clk_gate.mod
project_2_temp_1/rtlc_libs/work/clk_gate.mod.body
project_2_temp_1/rtlc_libs/work/main_bus.int
project_2_temp_1/rtlc_libs/work/main_bus.int.body
project_2_temp_1/rtlc_libs/work/rtlc_version_info
project_2_temp_1/rtlc.out/.rtlc_compile
project_2_temp_1/rtlc.out/.top
project_2_temp_1/rtlc.out/autotop.conf
project_2_temp_1/rtlc.out/legalmodmap.db
project_2_temp_1/rtlc.out/rtlc.args
project_2_temp_1/rtlc.out/rtlc_args1.file
project_2_temp_1/rtlc.out/vmw.mem_contents
project_2_temp_1/rtlc.out/INCR/emptymod.list
project_2_temp_1/rtlc.out/INCR/hier.list
project_2_temp_1/rtlc.out/INCR/incr_driver.log
project_2_temp_1/rtlc.out/INCR/incr_rtlc.log
project_2_temp_1/rtlc.out/FSM_REPORT/clk_gate.rpt
project_2_temp_1/rtlc.out/FSM_REPORT/sys.rpt
src/cpu.v
src/datapath.v
src/decode.v
src/defines.v
src/lib_fpga.v
src/mem.v
src/memory_board.v
src/mult.v
src/pio.v
src/register.v
src/rom.v
src/sasc_brg.v
src/sasc_fifo4.v
src/sasc_top.v
src/sys.v
src/test.v
src/timescale.v
src/top.v
src/uart.v
src/vdec_dsp16_decode.v
src/vdec_dsp16_regfile.v
src_sv/cpu.sv
src_sv/datapath.sv
src_sv/datapath.v
src_sv/decode.v
src_sv/defines.v
src_sv/lib_fpga.v
src_sv/main_bus.sv
src_sv/mem.v
src_sv/memory_board.sv
src_sv/mult.v
src_sv/pio.sv
src_sv/register.v
src_sv/sasc_brg.v
src_sv/sasc_fifo4.v
src_sv/sasc_top.v
src_sv/sys.sv
src_sv/timescale.v
src_sv/top.sv
src_sv/uart.sv
.jaguarc
precision.log
project_2.psp
setup_datapath.tcl
setup_sys.tcl
setup_top.tcl
project_2_temp_1/rtlc.out/INCR/tmp
project_2_temp_1/rtlc.out/INCR/AREA
project_2_temp_1/rtlc_libs/work
project_2_temp_1/rtlc.out/NM
project_2_temp_1/rtlc.out/NET
project_2_temp_1/rtlc.out/MEM
project_2_temp_1/rtlc.out/INCR
project_2_temp_1/rtlc.out/FSM_REPORT
project_2_temp_1/rtlc.out/EXEM_MACRO_DIR
project_2_temp_1/rtlc.out/depend
project_2_temp_1/rtlc_libs
project_2_temp_1/rtlc.out
project_2_impl_1
project_2_temp_1
src
src_sv
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