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文件名称:SPI_system

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.6mb
  • 已下载：
    0次
  • 提 供 者：
    wei ch******
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

This a SPI for DE_2 board.The file sampling frequency is 20Khz and board frequency used by this 27Mhz.The slaver chip is MCP2302 working under 3.3V.Finally the input analogue voltage for CH0 is between 0V and 3.3V -This is a SPI for DE_2 board.The file sampling frequency is 20Khz and board frequency used by this 27Mhz.The slaver chip is MCP2302 working under 3.3V.Finally the input analogue voltage for CH0 is between 0V and 3.3V.The specific report is also included in it
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SPI_assigment.docx
Verilog demonstation/clock_divider/clock_divider.asm.rpt
Verilog demonstation/clock_divider/clock_divider.done
Verilog demonstation/clock_divider/clock_divider.fit.rpt
Verilog demonstation/clock_divider/clock_divider.fit.summary
Verilog demonstation/clock_divider/clock_divider.flow.rpt
Verilog demonstation/clock_divider/clock_divider.map.rpt
Verilog demonstation/clock_divider/clock_divider.map.summary
Verilog demonstation/clock_divider/clock_divider.pin
Verilog demonstation/clock_divider/clock_divider.pof
Verilog demonstation/clock_divider/clock_divider.qpf
Verilog demonstation/clock_divider/clock_divider.qsf
Verilog demonstation/clock_divider/clock_divider.qws
Verilog demonstation/clock_divider/clock_divider.sim.rpt
Verilog demonstation/clock_divider/clock_divider.sof
Verilog demonstation/clock_divider/clock_divider.tan.rpt
Verilog demonstation/clock_divider/clock_divider.tan.summary
Verilog demonstation/clock_divider/clock_divider.v
Verilog demonstation/clock_divider/clock_divider.v.bak
Verilog demonstation/clock_divider/clock_divider.vwf
Verilog demonstation/clock_divider/db/clock_divider.(0).cnf.cdb
Verilog demonstation/clock_divider/db/clock_divider.(0).cnf.hdb
Verilog demonstation/clock_divider/db/clock_divider.asm.qmsg
Verilog demonstation/clock_divider/db/clock_divider.asm.rdb
Verilog demonstation/clock_divider/db/clock_divider.asm_labs.ddb
Verilog demonstation/clock_divider/db/clock_divider.cbx.xml
Verilog demonstation/clock_divider/db/clock_divider.cmp.bpm
Verilog demonstation/clock_divider/db/clock_divider.cmp.cdb
Verilog demonstation/clock_divider/db/clock_divider.cmp.ecobp
Verilog demonstation/clock_divider/db/clock_divider.cmp.hdb
Verilog demonstation/clock_divider/db/clock_divider.cmp.kpt
Verilog demonstation/clock_divider/db/clock_divider.cmp.logdb
Verilog demonstation/clock_divider/db/clock_divider.cmp.rdb
Verilog demonstation/clock_divider/db/clock_divider.cmp.tdb
Verilog demonstation/clock_divider/db/clock_divider.cmp0.ddb
Verilog demonstation/clock_divider/db/clock_divider.cmp_merge.kpt
Verilog demonstation/clock_divider/db/clock_divider.db_info
Verilog demonstation/clock_divider/db/clock_divider.eco.cdb
Verilog demonstation/clock_divider/db/clock_divider.eds_overflow
Verilog demonstation/clock_divider/db/clock_divider.fit.qmsg
Verilog demonstation/clock_divider/db/clock_divider.hier_info
Verilog demonstation/clock_divider/db/clock_divider.hif
Verilog demonstation/clock_divider/db/clock_divider.lpc.html
Verilog demonstation/clock_divider/db/clock_divider.lpc.rdb
Verilog demonstation/clock_divider/db/clock_divider.lpc.txt
Verilog demonstation/clock_divider/db/clock_divider.map.bpm
Verilog demonstation/clock_divider/db/clock_divider.map.cdb
Verilog demonstation/clock_divider/db/clock_divider.map.ecobp
Verilog demonstation/clock_divider/db/clock_divider.map.hdb
Verilog demonstation/clock_divider/db/clock_divider.map.kpt
Verilog demonstation/clock_divider/db/clock_divider.map.logdb
Verilog demonstation/clock_divider/db/clock_divider.map.qmsg
Verilog demonstation/clock_divider/db/clock_divider.map_bb.cdb
Verilog demonstation/clock_divider/db/clock_divider.map_bb.hdb
Verilog demonstation/clock_divider/db/clock_divider.map_bb.logdb
Verilog demonstation/clock_divider/db/clock_divider.pre_map.cdb
Verilog demonstation/clock_divider/db/clock_divider.pre_map.hdb
Verilog demonstation/clock_divider/db/clock_divider.rtlv.hdb
Verilog demonstation/clock_divider/db/clock_divider.rtlv_sg.cdb
Verilog demonstation/clock_divider/db/clock_divider.rtlv_sg_swap.cdb
Verilog demonstation/clock_divider/db/clock_divider.sgdiff.cdb
Verilog demonstation/clock_divider/db/clock_divider.sgdiff.hdb
Verilog demonstation/clock_divider/db/clock_divider.sim.cvwf
Verilog demonstation/clock_divider/db/clock_divider.sim.hdb
Verilog demonstation/clock_divider/db/clock_divider.sim.qmsg
Verilog demonstation/clock_divider/db/clock_divider.sim.rdb
Verilog demonstation/clock_divider/db/clock_divider.sld_design_entry.sci
Verilog demonstation/clock_divider/db/clock_divider.sld_design_entry_dsc.sci
Verilog demonstation/clock_divider/db/clock_divider.smart_action.txt
Verilog demonstation/clock_divider/db/clock_divider.smp_dump.txt
Verilog demonstation/clock_divider/db/clock_divider.syn_hier_info
Verilog demonstation/clock_divider/db/clock_divider.tan.qmsg
Verilog demonstation/clock_divider/db/clock_divider.tis_db_list.ddb
Verilog demonstation/clock_divider/db/clock_divider.tmw_info
Verilog demonstation/clock_divider/db/logic_util_heursitic.dat
Verilog demonstation/clock_divider/db/prev_cmp_clock_divider.qmsg
Verilog demonstation/clock_divider/db/prev_cmp_clock_divider.sim.qmsg
Verilog demonstation/clock_divider/db/wed.wsf
Verilog demonstation/clock_divider/incremental_db/compiled_partitions/clock_divider.root_partition.cmp.cdb
Verilog demonstation/clock_divider/incremental_db/compiled_partitions/clock_divider.root_partition.cmp.dfp
Verilog demonstation/clock_divider/incremental_db/compiled_partitions/clock_divider.root_partition.cmp.hdb
Verilog demonstation/clock_divider/incremental_db/compiled_partitions/clock_divider.root_partition.cmp

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