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文件名称:source
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FPGA中实现I2C接口的一个IP核，包含verilog及VHDL代码。方便迅速理解和开发I2C总线接口。-FPGA to implement an I2C interface IP core that contains verilog and VHDL code. Facilitate rapid understanding and development of I2C bus interface.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
source/verilog/i2c_master_bit_ctrl.v
source/verilog/i2c_master_byte_ctrl.v
source/verilog/i2c_master_defines.v
source/verilog/i2c_master_registers.v
source/verilog/i2c_master_wb_top.v
source/verilog/timescale.v
source/vhdl/i2c_master_bit_ctrl.vhd
source/vhdl/i2c_master_byte_ctrl.vhd
source/vhdl/i2c_master_registers.vhd
source/vhdl/i2c_master_wb_top.vhd
source/verilog
source/vhdl
source
source/verilog/i2c_master_byte_ctrl.v
source/verilog/i2c_master_defines.v
source/verilog/i2c_master_registers.v
source/verilog/i2c_master_wb_top.v
source/verilog/timescale.v
source/vhdl/i2c_master_bit_ctrl.vhd
source/vhdl/i2c_master_byte_ctrl.vhd
source/vhdl/i2c_master_registers.vhd
source/vhdl/i2c_master_wb_top.vhd
source/verilog
source/vhdl
source
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