DS-Verilog/DS/DS.prj
DS-Verilog/DS/说明.txt
DS-Verilog/DS/DS.prj.convert.7.3.bak
DS-Verilog/DS/component
DS-Verilog/DS/hdl/Adc.v
DS-Verilog/DS/hdl/SPI.v
DS-Verilog/DS/hdl/Distace.v
DS-Verilog/DS/hdl
DS-Verilog/DS/designer/impl1/Adc.tcl
DS-Verilog/DS/designer/impl1/Adc.ide_des
DS-Verilog/DS/designer/impl1/Distace.lok
DS-Verilog/DS/designer/impl1/Distace.adb
DS-Verilog/DS/designer/impl1/ada02724-1.tmp
DS-Verilog/DS/designer/impl1/Distace.adl
DS-Verilog/DS/designer/impl1/Adc.adb
DS-Verilog/DS/designer/impl1/designer.log
DS-Verilog/DS/designer/impl1/Adc.adl
DS-Verilog/DS/designer/impl1/Distace.tcl
DS-Verilog/DS/designer/impl1/Distace.ide_des
DS-Verilog/DS/designer/impl1/Distace-am.sdf
DS-Verilog/DS/designer/impl1/Distace.bit
DS-Verilog/DS/designer/impl1/Distace_ba.sdf
DS-Verilog/DS/designer/impl1/Distace_ba.v
DS-Verilog/DS/designer/impl1/Distace.vnm
DS-Verilog/DS/designer/impl1/flashpro.log
DS-Verilog/DS/designer/impl1/Distace.stp
DS-Verilog/DS/designer/impl1/Distace_fp/Distace.log
DS-Verilog/DS/designer/impl1/Distace_fp/Distace.pro
DS-Verilog/DS/designer/impl1/Distace_fp/projectData/Distace.stp
DS-Verilog/DS/designer/impl1/Distace_fp/projectData
DS-Verilog/DS/designer/impl1/Distace_fp
DS-Verilog/DS/designer/impl1/Distace.dtf/master.gcf
DS-Verilog/DS/designer/impl1/Distace.dtf/master-des.gcf
DS-Verilog/DS/designer/impl1/Distace.dtf/import.log
DS-Verilog/DS/designer/impl1/Distace.dtf/masks
DS-Verilog/DS/designer/impl1/Distace.dtf/floorplan.gcf
DS-Verilog/DS/designer/impl1/Distace.dtf/floorplan.gcf.old
DS-Verilog/DS/designer/impl1/Distace.dtf/place.log
DS-Verilog/DS/designer/impl1/Distace.dtf/last_placement.gcf
DS-Verilog/DS/designer/impl1/Distace.dtf/mem_plmt.gcf
DS-Verilog/DS/designer/impl1/Distace.dtf/masks.final
DS-Verilog/DS/designer/impl1/Distace.dtf/route.log
DS-Verilog/DS/designer/impl1/Distace.dtf/time.log
DS-Verilog/DS/designer/impl1/Distace.dtf/bitgen.log
DS-Verilog/DS/designer/impl1/Distace.dtf/initial_placement.gcf
DS-Verilog/DS/designer/impl1/Distace.dtf/floorplan-des.gcf
DS-Verilog/DS/designer/impl1/Distace.dtf
DS-Verilog/DS/designer/impl1/Adc.dtf/master.gcf
DS-Verilog/DS/designer/impl1/Adc.dtf/master-des.gcf
DS-Verilog/DS/designer/impl1/Adc.dtf/import.log
DS-Verilog/DS/designer/impl1/Adc.dtf/masks
DS-Verilog/DS/designer/impl1/Adc.dtf/inverted_ports
DS-Verilog/DS/designer/impl1/Adc.dtf/floorplan.gcf
DS-Verilog/DS/designer/impl1/Adc.dtf
DS-Verilog/DS/designer/impl1/simulation
DS-Verilog/DS/designer/impl1
DS-Verilog/DS/designer
DS-Verilog/DS/stimulus
DS-Verilog/DS/phy_synthesis
DS-Verilog/DS/synthesis/Distace.srr
DS-Verilog/DS/synthesis/stdout.log
DS-Verilog/DS/synthesis/Distace.tlg
DS-Verilog/DS/synthesis/Distace.srs
DS-Verilog/DS/synthesis/Distace_syn.prj
DS-Verilog/DS/synthesis/Distace_syn.prd
DS-Verilog/DS/synthesis/Distace.srd
DS-Verilog/DS/synthesis/Distace.srm
DS-Verilog/DS/synthesis/Adc.srr
DS-Verilog/DS/synthesis/Adc.tlg
DS-Verilog/DS/synthesis/Distace.map
DS-Verilog/DS/synthesis/Distace.edn
DS-Verilog/DS/synthesis/Distace.sdf
DS-Verilog/DS/synthesis/Distace_sdc.sdc
DS-Verilog/DS/synthesis/Distace.areasrr
DS-Verilog/DS/synthesis/Adc_syn.prj
DS-Verilog/DS/synthesis/traplog.tlg
DS-Verilog/DS/synthesis/.recordref
DS-Verilog/DS/synthesis/Adc.srd
DS-Verilog/DS/synthesis/Adc.srm
DS-Verilog/DS/synthesis/Adc.map
DS-Verilog/DS/synthesis/Adc.edn
DS-Verilog/DS/synthesis/Adc.sdf
DS-Verilog/DS/synthesis/Adc_sdc.sdc
DS-Verilog/DS/synthesis/Adc.areasrr
DS-Verilog/DS/synthesis/Adc_syn.prd
DS-Verilog/DS/synthesis/Adc.srs
DS-Verilog/DS/synthesis/syntmp/Adc.plg
DS-Verilog/DS/synthesis/syntmp/Adc.msg
DS-Verilog/DS/synthesis/syntmp/Distace.msg
DS-Verilog/DS/synthesis/syntmp/Distace.plg
DS-Verilog/DS/synthesis/syntmp
DS-Verilog/DS/synthesis
DS-Verilog/DS/simulation/meminit.dat
DS-Verilog/DS/simulation/modelsim.ini.sav
DS-Verilog/DS/simulation/modelsim.ini
DS-Verilog/DS/simulation
DS-Verilog/DS/coreconsole
DS-Verilog/DS/smartgen/smartgen.aws
DS-Verilog/DS/smartgen
DS-Verilog/DS/viewdraw/viewdraw.ini
DS-Verilog/DS/viewdraw/wir
DS-Verilog/DS/viewdraw/sym
DS-Verilog/DS/viewdraw/sch
DS-Verilog/DS/viewdraw/vf/project.lst
DS-Verilog/DS/viewdraw/vf
DS-Verilog/DS/viewdraw
DS-Verilog/DS/constraint
DS-Verilog/DS/hdl1/Distance.v
DS-Verilog/DS/hdl1/waveperl.log
DS-Verilog/DS/hdl1
DS-Verilog/DS
DS-Verilog