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文件名称:I2C
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- 上传时间：2012-11-16
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文件大小：28.32kb
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i2c设计VHDL和Verlog文件,提供给有需要的进行参考-i2c VHDL design files and Verlog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
rtl/CVS/Root
rtl/CVS/Repository
rtl/CVS/Template
rtl/CVS/Entries
rtl/CVS/Entries.Extra
rtl/verilog/CVS/Root
rtl/verilog/CVS/Repository
rtl/verilog/CVS/Template
rtl/verilog/CVS/Entries
rtl/verilog/CVS/Entries.Extra
rtl/verilog/i2c_master_bit_ctrl.v
rtl/verilog/i2c_master_byte_ctrl.v
rtl/verilog/i2c_master_defines.v
rtl/verilog/i2c_master_top.v
rtl/verilog/timescale.v
rtl/vhdl/CVS/Root
rtl/vhdl/CVS/Repository
rtl/vhdl/CVS/Template
rtl/vhdl/CVS/Entries
rtl/vhdl/CVS/Entries.Extra
rtl/vhdl/I2C.VHD
rtl/vhdl/i2c_master_bit_ctrl.vhd
rtl/vhdl/i2c_master_byte_ctrl.vhd
rtl/vhdl/i2c_master_top.vhd
rtl/vhdl/readme
rtl/vhdl/tst_ds1621.vhd
rtl/verilog/CVS
rtl/vhdl/CVS
rtl/CVS
rtl/verilog
rtl/vhdl
rtl
rtl/CVS/Repository
rtl/CVS/Template
rtl/CVS/Entries
rtl/CVS/Entries.Extra
rtl/verilog/CVS/Root
rtl/verilog/CVS/Repository
rtl/verilog/CVS/Template
rtl/verilog/CVS/Entries
rtl/verilog/CVS/Entries.Extra
rtl/verilog/i2c_master_bit_ctrl.v
rtl/verilog/i2c_master_byte_ctrl.v
rtl/verilog/i2c_master_defines.v
rtl/verilog/i2c_master_top.v
rtl/verilog/timescale.v
rtl/vhdl/CVS/Root
rtl/vhdl/CVS/Repository
rtl/vhdl/CVS/Template
rtl/vhdl/CVS/Entries
rtl/vhdl/CVS/Entries.Extra
rtl/vhdl/I2C.VHD
rtl/vhdl/i2c_master_bit_ctrl.vhd
rtl/vhdl/i2c_master_byte_ctrl.vhd
rtl/vhdl/i2c_master_top.vhd
rtl/vhdl/readme
rtl/vhdl/tst_ds1621.vhd
rtl/verilog/CVS
rtl/vhdl/CVS
rtl/CVS
rtl/verilog
rtl/vhdl
rtl
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