文件名称:Clk_Div
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- 上传时间:2012-11-16
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文件大小:359.97kb
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FPGA分频器的设计,通过修改参数值可以实现各种时钟频率信号。-Divider FPGA design can be achieved by modifying the parameter values of various clock frequency signal.
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下载文件列表
Clk_Div/clk_div.asm.rpt
Clk_Div/clk_div.done
Clk_Div/clk_div.eda.rpt
Clk_Div/clk_div.fit.rpt
Clk_Div/clk_div.fit.smsg
Clk_Div/clk_div.fit.summary
Clk_Div/clk_div.flow.rpt
Clk_Div/clk_div.map.rpt
Clk_Div/clk_div.map.summary
Clk_Div/clk_div.pin
Clk_Div/clk_div.pof
Clk_Div/clk_div.qpf
Clk_Div/clk_div.qsf
Clk_Div/clk_div.qws
Clk_Div/clk_div.saf
Clk_Div/clk_div.sim.rpt
Clk_Div/clk_div.sof
Clk_Div/clk_div.tan.rpt
Clk_Div/clk_div.tan.summary
Clk_Div/clk_div.v
Clk_Div/clk_div.v.bak
Clk_Div/clk_div.vwf
Clk_Div/clk_div_nativelink_simulation.rpt
Clk_Div/db/clk_div.(0).cnf.cdb
Clk_Div/db/clk_div.(0).cnf.hdb
Clk_Div/db/clk_div.asm.qmsg
Clk_Div/db/clk_div.asm_labs.ddb
Clk_Div/db/clk_div.cbx.xml
Clk_Div/db/clk_div.cmp.bpm
Clk_Div/db/clk_div.cmp.cdb
Clk_Div/db/clk_div.cmp.ecobp
Clk_Div/db/clk_div.cmp.hdb
Clk_Div/db/clk_div.cmp.kpt
Clk_Div/db/clk_div.cmp.logdb
Clk_Div/db/clk_div.cmp.rdb
Clk_Div/db/clk_div.cmp.tdb
Clk_Div/db/clk_div.cmp0.ddb
Clk_Div/db/clk_div.cmp2.ddb
Clk_Div/db/clk_div.cmp_merge.kpt
Clk_Div/db/clk_div.db_info
Clk_Div/db/clk_div.eco.cdb
Clk_Div/db/clk_div.eda.qmsg
Clk_Div/db/clk_div.eds_overflow
Clk_Div/db/clk_div.fit.qmsg
Clk_Div/db/clk_div.hier_info
Clk_Div/db/clk_div.hif
Clk_Div/db/clk_div.lpc.html
Clk_Div/db/clk_div.lpc.rdb
Clk_Div/db/clk_div.lpc.txt
Clk_Div/db/clk_div.map.bpm
Clk_Div/db/clk_div.map.cdb
Clk_Div/db/clk_div.map.ecobp
Clk_Div/db/clk_div.map.hdb
Clk_Div/db/clk_div.map.kpt
Clk_Div/db/clk_div.map.logdb
Clk_Div/db/clk_div.map.qmsg
Clk_Div/db/clk_div.map_bb.cdb
Clk_Div/db/clk_div.map_bb.hdb
Clk_Div/db/clk_div.map_bb.logdb
Clk_Div/db/clk_div.pre_map.cdb
Clk_Div/db/clk_div.pre_map.hdb
Clk_Div/db/clk_div.rtlv.hdb
Clk_Div/db/clk_div.rtlv_sg.cdb
Clk_Div/db/clk_div.rtlv_sg_swap.cdb
Clk_Div/db/clk_div.sgdiff.cdb
Clk_Div/db/clk_div.sgdiff.hdb
Clk_Div/db/clk_div.sim.cvwf
Clk_Div/db/clk_div.sim.hdb
Clk_Div/db/clk_div.sim.qmsg
Clk_Div/db/clk_div.sim.rdb
Clk_Div/db/clk_div.sld_design_entry.sci
Clk_Div/db/clk_div.sld_design_entry_dsc.sci
Clk_Div/db/clk_div.syn_hier_info
Clk_Div/db/clk_div.tan.qmsg
Clk_Div/db/clk_div.tis_db_list.ddb
Clk_Div/db/clk_div.tmw_info
Clk_Div/db/prev_cmp_clk_div.asm.qmsg
Clk_Div/db/prev_cmp_clk_div.fit.qmsg
Clk_Div/db/prev_cmp_clk_div.map.qmsg
Clk_Div/db/prev_cmp_clk_div.qmsg
Clk_Div/db/prev_cmp_clk_div.tan.qmsg
Clk_Div/db/wed.wsf
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.atm
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.dfp
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.hdbx
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.kpt
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.logdb
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.rcf
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.map.atm
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.map.dpi
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.map.hdbx
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.map.kpt
Clk_Div/incremental_db/README
Clk_Div/simulation/modelsim/clk_div.sft
Clk_Div/simulation/modelsim/clk_div.vo
Clk_Div/simulation/modelsim/clk_div.vt
Clk_Div/simulation/modelsim/clk_div_modelsim.xrf
Clk_Div/simulation/modelsim/clk_div_run_msim_gate_verilog.do
Clk_Div/simulation/modelsim/clk_div_run_msim_rtl_verilog.do
Clk_Div/simulation/modelsim/clk_div_run_msim_rtl_verilog.do.bak
Clk_Div/simulation/modelsim/clk_div_run_msim_rtl_verilog.do.bak1
Clk_Div/simulation/modelsim/clk_div_v.sdo
Clk_Div/simulation/modelsim/clk_div_v.sdo_typ.csd
Clk_Div/simulation/modelsim/gate_work/clk_div/verilog.psm
Clk_Div/simulation/modelsim/gate_work/clk_div/_primary.dat
Clk_Div/simulation/modelsim/gate_work/clk_div/_primary.dbs
Clk_Div/simulation/modelsim/gate_work/clk_div/_primary.vhd
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_check_tst/verilog.psm
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_check_tst/_primary.dat
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_check_tst/_primary.dbs
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_check_tst/_primary.vhd
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_sample_tst/verilog.psm
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_sample_tst/_primary.dat
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_sample_tst/_primary.dbs
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_sample_tst/_primary.vhd
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_vec_tst/verilog.psm
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_vec_tst/_primary.dat
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_vec_tst/_primary.dbs
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_vec_tst/_primary.vhd
Clk_Div/simulation/modelsim/gate_work/_info
Clk_Div/simulation/modelsim/gate_work/_vmake
Clk_Div/simulation/modelsim/msim_transcript
Clk_Div/simulation/modelsim/rtl_work/clk_div/verilog.psm
Clk_Div/simulation/modelsim/rtl_work/clk_div/_primary.dat
Clk_Div/simulation/modelsim/rtl_work/clk_div/_primary.dbs
Clk_Div/simulation/modelsim/rtl_work/clk_div/_primary.vhd
Clk_Div/simulation/modelsim/rtl_work/clk_div_vlg_check_tst/verilog.psm
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Clk_Div/clk_div.done
Clk_Div/clk_div.eda.rpt
Clk_Div/clk_div.fit.rpt
Clk_Div/clk_div.fit.smsg
Clk_Div/clk_div.fit.summary
Clk_Div/clk_div.flow.rpt
Clk_Div/clk_div.map.rpt
Clk_Div/clk_div.map.summary
Clk_Div/clk_div.pin
Clk_Div/clk_div.pof
Clk_Div/clk_div.qpf
Clk_Div/clk_div.qsf
Clk_Div/clk_div.qws
Clk_Div/clk_div.saf
Clk_Div/clk_div.sim.rpt
Clk_Div/clk_div.sof
Clk_Div/clk_div.tan.rpt
Clk_Div/clk_div.tan.summary
Clk_Div/clk_div.v
Clk_Div/clk_div.v.bak
Clk_Div/clk_div.vwf
Clk_Div/clk_div_nativelink_simulation.rpt
Clk_Div/db/clk_div.(0).cnf.cdb
Clk_Div/db/clk_div.(0).cnf.hdb
Clk_Div/db/clk_div.asm.qmsg
Clk_Div/db/clk_div.asm_labs.ddb
Clk_Div/db/clk_div.cbx.xml
Clk_Div/db/clk_div.cmp.bpm
Clk_Div/db/clk_div.cmp.cdb
Clk_Div/db/clk_div.cmp.ecobp
Clk_Div/db/clk_div.cmp.hdb
Clk_Div/db/clk_div.cmp.kpt
Clk_Div/db/clk_div.cmp.logdb
Clk_Div/db/clk_div.cmp.rdb
Clk_Div/db/clk_div.cmp.tdb
Clk_Div/db/clk_div.cmp0.ddb
Clk_Div/db/clk_div.cmp2.ddb
Clk_Div/db/clk_div.cmp_merge.kpt
Clk_Div/db/clk_div.db_info
Clk_Div/db/clk_div.eco.cdb
Clk_Div/db/clk_div.eda.qmsg
Clk_Div/db/clk_div.eds_overflow
Clk_Div/db/clk_div.fit.qmsg
Clk_Div/db/clk_div.hier_info
Clk_Div/db/clk_div.hif
Clk_Div/db/clk_div.lpc.html
Clk_Div/db/clk_div.lpc.rdb
Clk_Div/db/clk_div.lpc.txt
Clk_Div/db/clk_div.map.bpm
Clk_Div/db/clk_div.map.cdb
Clk_Div/db/clk_div.map.ecobp
Clk_Div/db/clk_div.map.hdb
Clk_Div/db/clk_div.map.kpt
Clk_Div/db/clk_div.map.logdb
Clk_Div/db/clk_div.map.qmsg
Clk_Div/db/clk_div.map_bb.cdb
Clk_Div/db/clk_div.map_bb.hdb
Clk_Div/db/clk_div.map_bb.logdb
Clk_Div/db/clk_div.pre_map.cdb
Clk_Div/db/clk_div.pre_map.hdb
Clk_Div/db/clk_div.rtlv.hdb
Clk_Div/db/clk_div.rtlv_sg.cdb
Clk_Div/db/clk_div.rtlv_sg_swap.cdb
Clk_Div/db/clk_div.sgdiff.cdb
Clk_Div/db/clk_div.sgdiff.hdb
Clk_Div/db/clk_div.sim.cvwf
Clk_Div/db/clk_div.sim.hdb
Clk_Div/db/clk_div.sim.qmsg
Clk_Div/db/clk_div.sim.rdb
Clk_Div/db/clk_div.sld_design_entry.sci
Clk_Div/db/clk_div.sld_design_entry_dsc.sci
Clk_Div/db/clk_div.syn_hier_info
Clk_Div/db/clk_div.tan.qmsg
Clk_Div/db/clk_div.tis_db_list.ddb
Clk_Div/db/clk_div.tmw_info
Clk_Div/db/prev_cmp_clk_div.asm.qmsg
Clk_Div/db/prev_cmp_clk_div.fit.qmsg
Clk_Div/db/prev_cmp_clk_div.map.qmsg
Clk_Div/db/prev_cmp_clk_div.qmsg
Clk_Div/db/prev_cmp_clk_div.tan.qmsg
Clk_Div/db/wed.wsf
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.atm
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.dfp
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.hdbx
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.kpt
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.logdb
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.cmp.rcf
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.map.atm
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.map.dpi
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.map.hdbx
Clk_Div/incremental_db/compiled_partitions/clk_div.root_partition.map.kpt
Clk_Div/incremental_db/README
Clk_Div/simulation/modelsim/clk_div.sft
Clk_Div/simulation/modelsim/clk_div.vo
Clk_Div/simulation/modelsim/clk_div.vt
Clk_Div/simulation/modelsim/clk_div_modelsim.xrf
Clk_Div/simulation/modelsim/clk_div_run_msim_gate_verilog.do
Clk_Div/simulation/modelsim/clk_div_run_msim_rtl_verilog.do
Clk_Div/simulation/modelsim/clk_div_run_msim_rtl_verilog.do.bak
Clk_Div/simulation/modelsim/clk_div_run_msim_rtl_verilog.do.bak1
Clk_Div/simulation/modelsim/clk_div_v.sdo
Clk_Div/simulation/modelsim/clk_div_v.sdo_typ.csd
Clk_Div/simulation/modelsim/gate_work/clk_div/verilog.psm
Clk_Div/simulation/modelsim/gate_work/clk_div/_primary.dat
Clk_Div/simulation/modelsim/gate_work/clk_div/_primary.dbs
Clk_Div/simulation/modelsim/gate_work/clk_div/_primary.vhd
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_check_tst/verilog.psm
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_check_tst/_primary.dat
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_check_tst/_primary.dbs
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_check_tst/_primary.vhd
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_sample_tst/verilog.psm
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_sample_tst/_primary.dat
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_sample_tst/_primary.dbs
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_sample_tst/_primary.vhd
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_vec_tst/verilog.psm
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_vec_tst/_primary.dat
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_vec_tst/_primary.dbs
Clk_Div/simulation/modelsim/gate_work/clk_div_vlg_vec_tst/_primary.vhd
Clk_Div/simulation/modelsim/gate_work/_info
Clk_Div/simulation/modelsim/gate_work/_vmake
Clk_Div/simulation/modelsim/msim_transcript
Clk_Div/simulation/modelsim/rtl_work/clk_div/verilog.psm
Clk_Div/simulation/modelsim/rtl_work/clk_div/_primary.dat
Clk_Div/simulation/modelsim/rtl_work/clk_div/_primary.dbs
Clk_Div/simulation/modelsim/rtl_work/clk_div/_primary.vhd
Clk_Div/simulation/modelsim/rtl_work/clk_div_vlg_check_tst/verilog.psm
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