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文件名称:185ed961-7850-4548-8157-bffde377e11d

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    2012-11-16
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    585.8kb
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这是基于fpga的led灯的点灯实验,可以作为fpga的入门实验,实验重点在于对595芯片的驱动的编写-This is based on fpga' s experiments led lights lighting can be used as entry fpga The experiment focuses on the preparation of 595 chip driver
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下载文件列表

ex2/seg7_verilog/db/prev_cmp_seg7.asm.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.eda.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.fit.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.map.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.sta.qmsg
ex2/seg7_verilog/db/prev_cmp_seg7.tan.qmsg
ex2/seg7_verilog/db/seg7.(0).cnf.cdb
ex2/seg7_verilog/db/seg7.(0).cnf.hdb
ex2/seg7_verilog/db/seg7.asm.qmsg
ex2/seg7_verilog/db/seg7.cbx.xml
ex2/seg7_verilog/db/seg7.cmp.bpm
ex2/seg7_verilog/db/seg7.cmp.cdb
ex2/seg7_verilog/db/seg7.cmp.ecobp
ex2/seg7_verilog/db/seg7.cmp.hdb
ex2/seg7_verilog/db/seg7.cmp.kpt
ex2/seg7_verilog/db/seg7.cmp.logdb
ex2/seg7_verilog/db/seg7.cmp.rdb
ex2/seg7_verilog/db/seg7.cmp0.ddb
ex2/seg7_verilog/db/seg7.cmp_merge.kpt
ex2/seg7_verilog/db/seg7.db_info
ex2/seg7_verilog/db/seg7.eco.cdb
ex2/seg7_verilog/db/seg7.eda.qmsg
ex2/seg7_verilog/db/seg7.fit.qmsg
ex2/seg7_verilog/db/seg7.hier_info
ex2/seg7_verilog/db/seg7.hif
ex2/seg7_verilog/db/seg7.lpc.html
ex2/seg7_verilog/db/seg7.lpc.rdb
ex2/seg7_verilog/db/seg7.lpc.txt
ex2/seg7_verilog/db/seg7.map.bpm
ex2/seg7_verilog/db/seg7.map.cdb
ex2/seg7_verilog/db/seg7.map.ecobp
ex2/seg7_verilog/db/seg7.map.hdb
ex2/seg7_verilog/db/seg7.map.kpt
ex2/seg7_verilog/db/seg7.map.logdb
ex2/seg7_verilog/db/seg7.map.qmsg
ex2/seg7_verilog/db/seg7.map_bb.cdb
ex2/seg7_verilog/db/seg7.map_bb.hdb
ex2/seg7_verilog/db/seg7.map_bb.logdb
ex2/seg7_verilog/db/seg7.pre_map.cdb
ex2/seg7_verilog/db/seg7.pre_map.hdb
ex2/seg7_verilog/db/seg7.rtlv.hdb
ex2/seg7_verilog/db/seg7.rtlv_sg.cdb
ex2/seg7_verilog/db/seg7.rtlv_sg_swap.cdb
ex2/seg7_verilog/db/seg7.sgdiff.cdb
ex2/seg7_verilog/db/seg7.sgdiff.hdb
ex2/seg7_verilog/db/seg7.sld_design_entry.sci
ex2/seg7_verilog/db/seg7.sld_design_entry_dsc.sci
ex2/seg7_verilog/db/seg7.sta.qmsg
ex2/seg7_verilog/db/seg7.sta.rdb
ex2/seg7_verilog/db/seg7.sta_cmp.8_slow.tdb
ex2/seg7_verilog/db/seg7.syn_hier_info
ex2/seg7_verilog/db/seg7.tis_db_list.ddb
ex2/seg7_verilog/db/seg7_global_asgn_op.abo
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.atm
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.dfp
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.hdbx
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.kpt
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.logdb
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.cmp.rcf
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.map.atm
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.map.dpi
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.map.hdbx
ex2/seg7_verilog/incremental_db/compiled_partitions/seg7.root_partition.map.kpt
ex2/seg7_verilog/incremental_db/README
ex2/seg7_verilog/seg7.asm.rpt
ex2/seg7_verilog/seg7.cdf
ex2/seg7_verilog/seg7.done
ex2/seg7_verilog/seg7.dpf
ex2/seg7_verilog/seg7.eda.rpt
ex2/seg7_verilog/seg7.fit.rpt
ex2/seg7_verilog/seg7.fit.smsg
ex2/seg7_verilog/seg7.fit.summary
ex2/seg7_verilog/seg7.flow.rpt
ex2/seg7_verilog/seg7.map.rpt
ex2/seg7_verilog/seg7.map.summary
ex2/seg7_verilog/seg7.pin
ex2/seg7_verilog/seg7.pof
ex2/seg7_verilog/seg7.qpf
ex2/seg7_verilog/seg7.qsf
ex2/seg7_verilog/seg7.qws
ex2/seg7_verilog/seg7.sdc
ex2/seg7_verilog/seg7.sof
ex2/seg7_verilog/seg7.sta.rpt
ex2/seg7_verilog/seg7.sta.summary
ex2/seg7_verilog/seg7.tan.rpt
ex2/seg7_verilog/seg7.tan.summary
ex2/seg7_verilog/seg7.v
ex2/seg7_verilog/seg7.v.bak
ex2/seg7_verilog/seg7_assignment_defaults.qdf
ex2/seg7_verilog/simulation/modelsim/altera_mf.v
ex2/seg7_verilog/simulation/modelsim/cyclone_atoms.v
ex2/seg7_verilog/simulation/modelsim/print_task.v
ex2/seg7_verilog/simulation/modelsim/seg7.sft
ex2/seg7_verilog/simulation/modelsim/seg7.vo
ex2/seg7_verilog/simulation/modelsim/seg7_modelsim.xrf
ex2/seg7_verilog/simulation/modelsim/seg7_v.sdo
ex2/seg7_verilog/simulation/modelsim/sys_ctrl_task.v
ex2/seg7_verilog/simulation/modelsim/tb_seg7.v
ex2/seg7_verilog/simulation/modelsim/tb_seg7.v.bak
ex2/seg7_verilog/simulation/modelsim/tb_seg7prj.cr.mti
ex2/seg7_verilog/simulation/modelsim/tb_seg7prj.mpf
ex2/Thumbs.db
ex2/seg7_verilog/incremental_db/compiled_partitions
ex2/seg7_verilog/simulation/modelsim
ex2/seg7_verilog/db
ex2/seg7_verilog/incremental_db
ex2/seg7_verilog/simulation
ex2/seg7_verilog
ex2

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