UART/UART.prj
UART/UART.prj.convert.7.3.bak
UART/viewdraw/viewdraw.ini
UART/viewdraw/vf/project.lst
UART/synthesis/.recordref
UART/synthesis/stdout.log
UART/synthesis/traplog.tlg
UART/synthesis/uart_test.areasrr
UART/synthesis/uart_test.edn
UART/synthesis/uart_test.fse
UART/synthesis/uart_test.map
UART/synthesis/uart_test.sdf
UART/synthesis/uart_test.srd
UART/synthesis/uart_test.srm
UART/synthesis/uart_test.srr
UART/synthesis/uart_test.srs
UART/synthesis/uart_test.tlg
UART/synthesis/uart_test_sdc.sdc
UART/synthesis/uart_test_syn.prd
UART/synthesis/uart_test_syn.prj
UART/synthesis/syntmp/sap.log
UART/synthesis/syntmp/uart_test.msg
UART/synthesis/syntmp/uart_test.plg
UART/smartgen/smartgen.aws
UART/simulation/meminit.dat
UART/simulation/modelsim.ini
UART/simulation/modelsim.ini.sav
UART/hdl/rec.v
UART/hdl/send.v
UART/hdl/uart_test.v
UART/designer/impl1/designer.log
UART/designer/impl1/uart_test.adb
UART/designer/impl1/uart_test.ide_des
UART/designer/impl1/uart_test.stp
UART/designer/impl1/uart_test.tcl
UART/designer/impl1/uart_test.dtf/verify.log
UART/designer/impl1/uart_test.dtf
UART/designer/impl1/simulation
UART/viewdraw/wir
UART/viewdraw/vf
UART/viewdraw/sym
UART/viewdraw/sch
UART/synthesis/syntmp
UART/designer/impl1
UART/viewdraw
UART/synthesis
UART/stimulus
UART/smartgen
UART/simulation
UART/phy_synthesis
UART/hdl
UART/designer
UART/coreconsole
UART/constraint
UART/component
UART