文件名称:rs232_UART
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- 上传时间:2012-11-16
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文件大小:499.97kb
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已下载:0次
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相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
RS232通讯程序,已经调试通过,可以直接使用。-RS232 communication program, has been through debugging, can be used directly.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UART/UART.prj
UART/UART.prj.convert.7.3.bak
UART/viewdraw/viewdraw.ini
UART/viewdraw/vf/project.lst
UART/synthesis/.recordref
UART/synthesis/stdout.log
UART/synthesis/traplog.tlg
UART/synthesis/uart_test.areasrr
UART/synthesis/uart_test.edn
UART/synthesis/uart_test.fse
UART/synthesis/uart_test.map
UART/synthesis/uart_test.sdf
UART/synthesis/uart_test.srd
UART/synthesis/uart_test.srm
UART/synthesis/uart_test.srr
UART/synthesis/uart_test.srs
UART/synthesis/uart_test.tlg
UART/synthesis/uart_test_sdc.sdc
UART/synthesis/uart_test_syn.prd
UART/synthesis/uart_test_syn.prj
UART/synthesis/syntmp/sap.log
UART/synthesis/syntmp/uart_test.msg
UART/synthesis/syntmp/uart_test.plg
UART/smartgen/smartgen.aws
UART/simulation/meminit.dat
UART/simulation/modelsim.ini
UART/simulation/modelsim.ini.sav
UART/hdl/rec.v
UART/hdl/send.v
UART/hdl/uart_test.v
UART/designer/impl1/designer.log
UART/designer/impl1/uart_test.adb
UART/designer/impl1/uart_test.ide_des
UART/designer/impl1/uart_test.stp
UART/designer/impl1/uart_test.tcl
UART/designer/impl1/uart_test.dtf/verify.log
UART/designer/impl1/uart_test.dtf
UART/designer/impl1/simulation
UART/viewdraw/wir
UART/viewdraw/vf
UART/viewdraw/sym
UART/viewdraw/sch
UART/synthesis/syntmp
UART/designer/impl1
UART/viewdraw
UART/synthesis
UART/stimulus
UART/smartgen
UART/simulation
UART/phy_synthesis
UART/hdl
UART/designer
UART/coreconsole
UART/constraint
UART/component
UART
rs232_UART/UART/designer/impl1/designer.log
rs232_UART/UART/designer/impl1/uart_test.adb
rs232_UART/UART/designer/impl1/uart_test.dtf/verify.log
rs232_UART/UART/designer/impl1/uart_test.ide_des
rs232_UART/UART/designer/impl1/uart_test.stp
rs232_UART/UART/designer/impl1/uart_test.tcl
rs232_UART/UART/hdl/rec.v
rs232_UART/UART/hdl/send.v
rs232_UART/UART/hdl/uart_test.v
rs232_UART/UART/simulation/meminit.dat
rs232_UART/UART/simulation/modelsim.ini
rs232_UART/UART/simulation/modelsim.ini.sav
rs232_UART/UART/smartgen/smartgen.aws
rs232_UART/UART/synthesis/.recordref
rs232_UART/UART/synthesis/stdout.log
rs232_UART/UART/synthesis/syntmp/sap.log
rs232_UART/UART/synthesis/syntmp/uart_test.msg
rs232_UART/UART/synthesis/syntmp/uart_test.plg
rs232_UART/UART/synthesis/traplog.tlg
rs232_UART/UART/synthesis/uart_test.areasrr
rs232_UART/UART/synthesis/uart_test.edn
rs232_UART/UART/synthesis/uart_test.fse
rs232_UART/UART/synthesis/uart_test.map
rs232_UART/UART/synthesis/uart_test.sdf
rs232_UART/UART/synthesis/uart_test.srd
rs232_UART/UART/synthesis/uart_test.srm
rs232_UART/UART/synthesis/uart_test.srr
rs232_UART/UART/synthesis/uart_test.srs
rs232_UART/UART/synthesis/uart_test.tlg
rs232_UART/UART/synthesis/uart_test_sdc.sdc
rs232_UART/UART/synthesis/uart_test_syn.prd
rs232_UART/UART/synthesis/uart_test_syn.prj
rs232_UART/UART/UART.prj
rs232_UART/UART/UART.prj.convert.7.3.bak
rs232_UART/UART/viewdraw/vf/project.lst
rs232_UART/UART/viewdraw/viewdraw.ini
rs232_UART/waveperl.log
rs232_UART/UART/designer/impl1/simulation
rs232_UART/UART/designer/impl1/uart_test.dtf
rs232_UART/UART/designer/impl1
rs232_UART/UART/synthesis/syntmp
rs232_UART/UART/viewdraw/sch
rs232_UART/UART/viewdraw/sym
rs232_UART/UART/viewdraw/vf
rs232_UART/UART/viewdraw/wir
rs232_UART/UART/component
rs232_UART/UART/constraint
rs232_UART/UART/coreconsole
rs232_UART/UART/designer
rs232_UART/UART/hdl
rs232_UART/UART/phy_synthesis
rs232_UART/UART/simulation
rs232_UART/UART/smartgen
rs232_UART/UART/stimulus
rs232_UART/UART/synthesis
rs232_UART/UART/viewdraw
rs232_UART/UART
rs232_UART
UART/UART.prj.convert.7.3.bak
UART/viewdraw/viewdraw.ini
UART/viewdraw/vf/project.lst
UART/synthesis/.recordref
UART/synthesis/stdout.log
UART/synthesis/traplog.tlg
UART/synthesis/uart_test.areasrr
UART/synthesis/uart_test.edn
UART/synthesis/uart_test.fse
UART/synthesis/uart_test.map
UART/synthesis/uart_test.sdf
UART/synthesis/uart_test.srd
UART/synthesis/uart_test.srm
UART/synthesis/uart_test.srr
UART/synthesis/uart_test.srs
UART/synthesis/uart_test.tlg
UART/synthesis/uart_test_sdc.sdc
UART/synthesis/uart_test_syn.prd
UART/synthesis/uart_test_syn.prj
UART/synthesis/syntmp/sap.log
UART/synthesis/syntmp/uart_test.msg
UART/synthesis/syntmp/uart_test.plg
UART/smartgen/smartgen.aws
UART/simulation/meminit.dat
UART/simulation/modelsim.ini
UART/simulation/modelsim.ini.sav
UART/hdl/rec.v
UART/hdl/send.v
UART/hdl/uart_test.v
UART/designer/impl1/designer.log
UART/designer/impl1/uart_test.adb
UART/designer/impl1/uart_test.ide_des
UART/designer/impl1/uart_test.stp
UART/designer/impl1/uart_test.tcl
UART/designer/impl1/uart_test.dtf/verify.log
UART/designer/impl1/uart_test.dtf
UART/designer/impl1/simulation
UART/viewdraw/wir
UART/viewdraw/vf
UART/viewdraw/sym
UART/viewdraw/sch
UART/synthesis/syntmp
UART/designer/impl1
UART/viewdraw
UART/synthesis
UART/stimulus
UART/smartgen
UART/simulation
UART/phy_synthesis
UART/hdl
UART/designer
UART/coreconsole
UART/constraint
UART/component
UART
rs232_UART/UART/designer/impl1/designer.log
rs232_UART/UART/designer/impl1/uart_test.adb
rs232_UART/UART/designer/impl1/uart_test.dtf/verify.log
rs232_UART/UART/designer/impl1/uart_test.ide_des
rs232_UART/UART/designer/impl1/uart_test.stp
rs232_UART/UART/designer/impl1/uart_test.tcl
rs232_UART/UART/hdl/rec.v
rs232_UART/UART/hdl/send.v
rs232_UART/UART/hdl/uart_test.v
rs232_UART/UART/simulation/meminit.dat
rs232_UART/UART/simulation/modelsim.ini
rs232_UART/UART/simulation/modelsim.ini.sav
rs232_UART/UART/smartgen/smartgen.aws
rs232_UART/UART/synthesis/.recordref
rs232_UART/UART/synthesis/stdout.log
rs232_UART/UART/synthesis/syntmp/sap.log
rs232_UART/UART/synthesis/syntmp/uart_test.msg
rs232_UART/UART/synthesis/syntmp/uart_test.plg
rs232_UART/UART/synthesis/traplog.tlg
rs232_UART/UART/synthesis/uart_test.areasrr
rs232_UART/UART/synthesis/uart_test.edn
rs232_UART/UART/synthesis/uart_test.fse
rs232_UART/UART/synthesis/uart_test.map
rs232_UART/UART/synthesis/uart_test.sdf
rs232_UART/UART/synthesis/uart_test.srd
rs232_UART/UART/synthesis/uart_test.srm
rs232_UART/UART/synthesis/uart_test.srr
rs232_UART/UART/synthesis/uart_test.srs
rs232_UART/UART/synthesis/uart_test.tlg
rs232_UART/UART/synthesis/uart_test_sdc.sdc
rs232_UART/UART/synthesis/uart_test_syn.prd
rs232_UART/UART/synthesis/uart_test_syn.prj
rs232_UART/UART/UART.prj
rs232_UART/UART/UART.prj.convert.7.3.bak
rs232_UART/UART/viewdraw/vf/project.lst
rs232_UART/UART/viewdraw/viewdraw.ini
rs232_UART/waveperl.log
rs232_UART/UART/designer/impl1/simulation
rs232_UART/UART/designer/impl1/uart_test.dtf
rs232_UART/UART/designer/impl1
rs232_UART/UART/synthesis/syntmp
rs232_UART/UART/viewdraw/sch
rs232_UART/UART/viewdraw/sym
rs232_UART/UART/viewdraw/vf
rs232_UART/UART/viewdraw/wir
rs232_UART/UART/component
rs232_UART/UART/constraint
rs232_UART/UART/coreconsole
rs232_UART/UART/designer
rs232_UART/UART/hdl
rs232_UART/UART/phy_synthesis
rs232_UART/UART/simulation
rs232_UART/UART/smartgen
rs232_UART/UART/stimulus
rs232_UART/UART/synthesis
rs232_UART/UART/viewdraw
rs232_UART/UART
rs232_UART
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