文件名称:uart
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- 上传时间:2012-11-16
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文件大小:196.58kb
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用verilog编写的uart代码,比较适合初学者练练手,包含初始化,收发等模块-Written code with verilog uart, more suitable for beginners practice your hand, including initialization, sending and receiving modules
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart/bd/my_uart_top.(0).cnf.cdb
uart/bd/my_uart_top.(0).cnf.hdb
uart/bd/my_uart_top.(1).cnf.cdb
uart/bd/my_uart_top.(1).cnf.hdb
uart/bd/my_uart_top.(2).cnf.cdb
uart/bd/my_uart_top.(2).cnf.hdb
uart/bd/my_uart_top.(3).cnf.cdb
uart/bd/my_uart_top.(3).cnf.hdb
uart/bd/my_uart_top.asm.qmsg
uart/bd/my_uart_top.cbx.xml
uart/bd/my_uart_top.cmp.bpm
uart/bd/my_uart_top.cmp.cdb
uart/bd/my_uart_top.cmp.ecobp
uart/bd/my_uart_top.cmp.hdb
uart/bd/my_uart_top.cmp.kpt
uart/bd/my_uart_top.cmp.logdb
uart/bd/my_uart_top.cmp.rdb
uart/bd/my_uart_top.cmp.tdb
uart/bd/my_uart_top.cmp0.ddb
uart/bd/my_uart_top.cmp_merge.kpt
uart/bd/my_uart_top.db_info
uart/bd/my_uart_top.eco.cdb
uart/bd/my_uart_top.fit.qmsg
uart/bd/my_uart_top.hier_info
uart/bd/my_uart_top.hif
uart/bd/my_uart_top.lpc.html
uart/bd/my_uart_top.lpc.rdb
uart/bd/my_uart_top.lpc.txt
uart/bd/my_uart_top.map.bpm
uart/bd/my_uart_top.map.cdb
uart/bd/my_uart_top.map.ecobp
uart/bd/my_uart_top.map.hdb
uart/bd/my_uart_top.map.kpt
uart/bd/my_uart_top.map.logdb
uart/bd/my_uart_top.map.qmsg
uart/bd/my_uart_top.map_bb.cdb
uart/bd/my_uart_top.map_bb.hdb
uart/bd/my_uart_top.map_bb.logdb
uart/bd/my_uart_top.pre_map.cdb
uart/bd/my_uart_top.pre_map.hdb
uart/bd/my_uart_top.rtlv.hdb
uart/bd/my_uart_top.rtlv_sg.cdb
uart/bd/my_uart_top.rtlv_sg_swap.cdb
uart/bd/my_uart_top.sgdiff.cdb
uart/bd/my_uart_top.sgdiff.hdb
uart/bd/my_uart_top.sld_design_entry.sci
uart/bd/my_uart_top.sld_design_entry_dsc.sci
uart/bd/my_uart_top.syn_hier_info
uart/bd/my_uart_top.tan.qmsg
uart/bd/my_uart_top.tis_db_list.ddb
uart/bd/my_uart_top.tmw_info
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.atm
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.dfp
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.hdbx
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.kpt
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.logdb
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.rcf
uart/incremental/compiled_partitions/my_uart_top.root_partition.map.atm
uart/incremental/compiled_partitions/my_uart_top.root_partition.map.dpi
uart/incremental/compiled_partitions/my_uart_top.root_partition.map.hdbx
uart/incremental/compiled_partitions/my_uart_top.root_partition.map.kpt
uart/incremental/README
uart/simulation/modelsim/modelsim.ini
uart/simulation/modelsim/msim_transcript
uart/simulation/modelsim/my_uart_top_run_msim_rtl_verilog.do
uart/simulation/modelsim/my_uart_top_run_msim_rtl_verilog.do.bak
uart/simulation/modelsim/rtl_work/my_uart_rx/verilog.psm
uart/simulation/modelsim/rtl_work/my_uart_rx/_primary.dat
uart/simulation/modelsim/rtl_work/my_uart_rx/_primary.dbs
uart/simulation/modelsim/rtl_work/my_uart_rx/_primary.vhd
uart/simulation/modelsim/rtl_work/my_uart_top/verilog.psm
uart/simulation/modelsim/rtl_work/my_uart_top/_primary.dat
uart/simulation/modelsim/rtl_work/my_uart_top/_primary.dbs
uart/simulation/modelsim/rtl_work/my_uart_top/_primary.vhd
uart/simulation/modelsim/rtl_work/my_uart_tx/verilog.psm
uart/simulation/modelsim/rtl_work/my_uart_tx/_primary.dat
uart/simulation/modelsim/rtl_work/my_uart_tx/_primary.dbs
uart/simulation/modelsim/rtl_work/my_uart_tx/_primary.vhd
uart/simulation/modelsim/rtl_work/speed_select/verilog.psm
uart/simulation/modelsim/rtl_work/speed_select/_primary.dat
uart/simulation/modelsim/rtl_work/speed_select/_primary.dbs
uart/simulation/modelsim/rtl_work/speed_select/_primary.vhd
uart/simulation/modelsim/rtl_work/_info
uart/simulation/modelsim/rtl_work/_vmake
uart/speedselect.v
uart/uart_rx.v
uart/uart_top.asm.rpt
uart/uart_top.done
uart/uart_top.fit.rpt
uart/uart_top.fit.summary
uart/uart_top.flow.rpt
uart/uart_top.map.rpt
uart/uart_top.map.summary
uart/uart_top.pin
uart/uart_top.pof
uart/uart_top.qpf
uart/uart_top.qsf
uart/uart_top.qws
uart/uart_top.sof
uart/uart_top.tan.rpt
uart/uart_top.v
uart/uart_top_nativelink_simulation.rpt
uart/uart_tx.v
uart/simulation/modelsim/rtl_work/my_uart_rx
uart/simulation/modelsim/rtl_work/my_uart_top
uart/simulation/modelsim/rtl_work/my_uart_tx
uart/simulation/modelsim/rtl_work/speed_select
uart/simulation/modelsim/rtl_work/_temp
uart/simulation/modelsim/rtl_work
uart/incremental/compiled_partitions
uart/simulation/modelsim
uart/bd
uart/incremental
uart/simulation
uart
uart/bd/my_uart_top.(0).cnf.hdb
uart/bd/my_uart_top.(1).cnf.cdb
uart/bd/my_uart_top.(1).cnf.hdb
uart/bd/my_uart_top.(2).cnf.cdb
uart/bd/my_uart_top.(2).cnf.hdb
uart/bd/my_uart_top.(3).cnf.cdb
uart/bd/my_uart_top.(3).cnf.hdb
uart/bd/my_uart_top.asm.qmsg
uart/bd/my_uart_top.cbx.xml
uart/bd/my_uart_top.cmp.bpm
uart/bd/my_uart_top.cmp.cdb
uart/bd/my_uart_top.cmp.ecobp
uart/bd/my_uart_top.cmp.hdb
uart/bd/my_uart_top.cmp.kpt
uart/bd/my_uart_top.cmp.logdb
uart/bd/my_uart_top.cmp.rdb
uart/bd/my_uart_top.cmp.tdb
uart/bd/my_uart_top.cmp0.ddb
uart/bd/my_uart_top.cmp_merge.kpt
uart/bd/my_uart_top.db_info
uart/bd/my_uart_top.eco.cdb
uart/bd/my_uart_top.fit.qmsg
uart/bd/my_uart_top.hier_info
uart/bd/my_uart_top.hif
uart/bd/my_uart_top.lpc.html
uart/bd/my_uart_top.lpc.rdb
uart/bd/my_uart_top.lpc.txt
uart/bd/my_uart_top.map.bpm
uart/bd/my_uart_top.map.cdb
uart/bd/my_uart_top.map.ecobp
uart/bd/my_uart_top.map.hdb
uart/bd/my_uart_top.map.kpt
uart/bd/my_uart_top.map.logdb
uart/bd/my_uart_top.map.qmsg
uart/bd/my_uart_top.map_bb.cdb
uart/bd/my_uart_top.map_bb.hdb
uart/bd/my_uart_top.map_bb.logdb
uart/bd/my_uart_top.pre_map.cdb
uart/bd/my_uart_top.pre_map.hdb
uart/bd/my_uart_top.rtlv.hdb
uart/bd/my_uart_top.rtlv_sg.cdb
uart/bd/my_uart_top.rtlv_sg_swap.cdb
uart/bd/my_uart_top.sgdiff.cdb
uart/bd/my_uart_top.sgdiff.hdb
uart/bd/my_uart_top.sld_design_entry.sci
uart/bd/my_uart_top.sld_design_entry_dsc.sci
uart/bd/my_uart_top.syn_hier_info
uart/bd/my_uart_top.tan.qmsg
uart/bd/my_uart_top.tis_db_list.ddb
uart/bd/my_uart_top.tmw_info
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.atm
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.dfp
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.hdbx
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.kpt
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.logdb
uart/incremental/compiled_partitions/my_uart_top.root_partition.cmp.rcf
uart/incremental/compiled_partitions/my_uart_top.root_partition.map.atm
uart/incremental/compiled_partitions/my_uart_top.root_partition.map.dpi
uart/incremental/compiled_partitions/my_uart_top.root_partition.map.hdbx
uart/incremental/compiled_partitions/my_uart_top.root_partition.map.kpt
uart/incremental/README
uart/simulation/modelsim/modelsim.ini
uart/simulation/modelsim/msim_transcript
uart/simulation/modelsim/my_uart_top_run_msim_rtl_verilog.do
uart/simulation/modelsim/my_uart_top_run_msim_rtl_verilog.do.bak
uart/simulation/modelsim/rtl_work/my_uart_rx/verilog.psm
uart/simulation/modelsim/rtl_work/my_uart_rx/_primary.dat
uart/simulation/modelsim/rtl_work/my_uart_rx/_primary.dbs
uart/simulation/modelsim/rtl_work/my_uart_rx/_primary.vhd
uart/simulation/modelsim/rtl_work/my_uart_top/verilog.psm
uart/simulation/modelsim/rtl_work/my_uart_top/_primary.dat
uart/simulation/modelsim/rtl_work/my_uart_top/_primary.dbs
uart/simulation/modelsim/rtl_work/my_uart_top/_primary.vhd
uart/simulation/modelsim/rtl_work/my_uart_tx/verilog.psm
uart/simulation/modelsim/rtl_work/my_uart_tx/_primary.dat
uart/simulation/modelsim/rtl_work/my_uart_tx/_primary.dbs
uart/simulation/modelsim/rtl_work/my_uart_tx/_primary.vhd
uart/simulation/modelsim/rtl_work/speed_select/verilog.psm
uart/simulation/modelsim/rtl_work/speed_select/_primary.dat
uart/simulation/modelsim/rtl_work/speed_select/_primary.dbs
uart/simulation/modelsim/rtl_work/speed_select/_primary.vhd
uart/simulation/modelsim/rtl_work/_info
uart/simulation/modelsim/rtl_work/_vmake
uart/speedselect.v
uart/uart_rx.v
uart/uart_top.asm.rpt
uart/uart_top.done
uart/uart_top.fit.rpt
uart/uart_top.fit.summary
uart/uart_top.flow.rpt
uart/uart_top.map.rpt
uart/uart_top.map.summary
uart/uart_top.pin
uart/uart_top.pof
uart/uart_top.qpf
uart/uart_top.qsf
uart/uart_top.qws
uart/uart_top.sof
uart/uart_top.tan.rpt
uart/uart_top.v
uart/uart_top_nativelink_simulation.rpt
uart/uart_tx.v
uart/simulation/modelsim/rtl_work/my_uart_rx
uart/simulation/modelsim/rtl_work/my_uart_top
uart/simulation/modelsim/rtl_work/my_uart_tx
uart/simulation/modelsim/rtl_work/speed_select
uart/simulation/modelsim/rtl_work/_temp
uart/simulation/modelsim/rtl_work
uart/incremental/compiled_partitions
uart/simulation/modelsim
uart/bd
uart/incremental
uart/simulation
uart
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