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文件名称:AD_1

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.02mb
  • 已下载：
    0次
  • 提 供 者：
    朱***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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基于FPGA的AD转换，AD芯片是TLC549，verilog-FPGA AD verilog
相关搜索： fpga AD verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

AD_1/AD_1.asm.rpt
AD_1/AD_1.cdf
AD_1/AD_1.done
AD_1/AD_1.eda.rpt
AD_1/AD_1.fit.rpt
AD_1/AD_1.fit.smsg
AD_1/AD_1.fit.summary
AD_1/AD_1.flow.rpt
AD_1/AD_1.jdi
AD_1/AD_1.map.rpt
AD_1/AD_1.map.smsg
AD_1/AD_1.map.summary
AD_1/AD_1.pin
AD_1/AD_1.pof
AD_1/AD_1.qpf
AD_1/AD_1.qsf
AD_1/AD_1.sof
AD_1/AD_1.sta.rpt
AD_1/AD_1.sta.summary
AD_1/AD_1.v
AD_1/AD_1.v.bak
AD_1/AD_1_nativelink_simulation.rpt
AD_1/AD_1_top.v
AD_1/AD_1_top.v.bak
AD_1/db/add_sub_lkc.tdf
AD_1/db/add_sub_mkc.tdf
AD_1/db/AD_1.(0).cnf.cdb
AD_1/db/AD_1.(0).cnf.hdb
AD_1/db/AD_1.(1).cnf.cdb
AD_1/db/AD_1.(1).cnf.hdb
AD_1/db/AD_1.(10).cnf.cdb
AD_1/db/AD_1.(10).cnf.hdb
AD_1/db/AD_1.(11).cnf.cdb
AD_1/db/AD_1.(11).cnf.hdb
AD_1/db/AD_1.(12).cnf.cdb
AD_1/db/AD_1.(12).cnf.hdb
AD_1/db/AD_1.(13).cnf.cdb
AD_1/db/AD_1.(13).cnf.hdb
AD_1/db/AD_1.(14).cnf.cdb
AD_1/db/AD_1.(14).cnf.hdb
AD_1/db/AD_1.(15).cnf.cdb
AD_1/db/AD_1.(15).cnf.hdb
AD_1/db/AD_1.(16).cnf.cdb
AD_1/db/AD_1.(16).cnf.hdb
AD_1/db/AD_1.(17).cnf.cdb
AD_1/db/AD_1.(17).cnf.hdb
AD_1/db/AD_1.(18).cnf.cdb
AD_1/db/AD_1.(18).cnf.hdb
AD_1/db/AD_1.(19).cnf.cdb
AD_1/db/AD_1.(19).cnf.hdb
AD_1/db/AD_1.(2).cnf.cdb
AD_1/db/AD_1.(2).cnf.hdb
AD_1/db/AD_1.(20).cnf.cdb
AD_1/db/AD_1.(20).cnf.hdb
AD_1/db/AD_1.(21).cnf.cdb
AD_1/db/AD_1.(21).cnf.hdb
AD_1/db/AD_1.(22).cnf.cdb
AD_1/db/AD_1.(22).cnf.hdb
AD_1/db/AD_1.(3).cnf.cdb
AD_1/db/AD_1.(3).cnf.hdb
AD_1/db/AD_1.(4).cnf.cdb
AD_1/db/AD_1.(4).cnf.hdb
AD_1/db/AD_1.(5).cnf.cdb
AD_1/db/AD_1.(5).cnf.hdb
AD_1/db/AD_1.(6).cnf.cdb
AD_1/db/AD_1.(6).cnf.hdb
AD_1/db/AD_1.(7).cnf.cdb
AD_1/db/AD_1.(7).cnf.hdb
AD_1/db/AD_1.(8).cnf.cdb
AD_1/db/AD_1.(8).cnf.hdb
AD_1/db/AD_1.(9).cnf.cdb
AD_1/db/AD_1.(9).cnf.hdb
AD_1/db/AD_1.amm.cdb
AD_1/db/AD_1.asm.qmsg
AD_1/db/AD_1.asm.rdb
AD_1/db/AD_1.asm_labs.ddb
AD_1/db/AD_1.cbx.xml
AD_1/db/AD_1.cmp.bpm
AD_1/db/AD_1.cmp.cdb
AD_1/db/AD_1.cmp.hdb
AD_1/db/AD_1.cmp.kpt
AD_1/db/AD_1.cmp.logdb
AD_1/db/AD_1.cmp.rdb
AD_1/db/AD_1.cmp0.ddb
AD_1/db/AD_1.cmp1.ddb
AD_1/db/AD_1.cmp2.ddb
AD_1/db/AD_1.cmp_merge.kpt
AD_1/db/AD_1.db_info
AD_1/db/AD_1.eda.qmsg
AD_1/db/AD_1.fit.qmsg
AD_1/db/AD_1.hier_info
AD_1/db/AD_1.hif
AD_1/db/AD_1.idb.cdb
AD_1/db/AD_1.lpc.html
AD_1/db/AD_1.lpc.rdb
AD_1/db/AD_1.lpc.txt
AD_1/db/AD_1.map.bpm
AD_1/db/AD_1.map.cdb
AD_1/db/AD_1.map.hdb
AD_1/db/AD_1.map.kpt
AD_1/db/AD_1.map.logdb
AD_1/db/AD_1.map.qmsg
AD_1/db/AD_1.map_bb.cdb
AD_1/db/AD_1.map_bb.hdb
AD_1/db/AD_1.map_bb.logdb
AD_1/db/AD_1.pre_map.cdb
AD_1/db/AD_1.pre_map.hdb
AD_1/db/AD_1.root_partition.map.reg_db.cdb
AD_1/db/AD_1.rtlv.hdb
AD_1/db/AD_1.rtlv_sg.cdb
AD_1/db/AD_1.rtlv_sg_swap.cdb
AD_1/db/AD_1.sgdiff.cdb
AD_1/db/AD_1.sgdiff.hdb
AD_1/db/AD_1.sld_design_entry.sci
AD_1/db/AD_1.sld_design_entry_dsc.sci
AD_1/db/AD_1.smart_action.txt
AD_1/db/AD_1.smp_dump.txt
AD_1/db/AD_1.sta.qmsg
AD_1/db/AD_1.sta.rdb
AD_1/db/AD_1.sta_cmp.8_slow.tdb
AD_1/db/AD_1.syn_hier_info
AD_1/db/AD_1.tis_db_list.ddb
AD_1/db/AD_1.tmw_info
AD_1/db/alt_u_div_mve.tdf
AD_1/db/alt_u_div_ove.tdf
AD_1/db/alt_u_div_uve.tdf
AD_1/db/logic_util_heursitic.dat
AD_1/db/lpm_divide_0dm.tdf
AD_1/db/lpm_divide_1dm.tdf
AD_1/db/lpm_divide_45m.tdf
AD_1/db/lpm_divide_4dm.tdf
AD_1/db/lpm_divide_75m.tdf
AD_1/db/prev_cmp_AD_1.qmsg
AD_1/db/sign_div_unsign_akh.tdf
AD_1/db/sign_div_unsign_bkh.tdf
AD_1/db/sign_div_unsign_ekh.tdf
AD_1/incremental_db/compiled_partitions/AD_1.db_info
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.cmp.cdb
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.cmp.dfp
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.cmp.hdb
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.cmp.kpt
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.cmp.logdb
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.cmp.rcfdb
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.map.cdb
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.map.dpi
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.map.hbdb.cdb
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.map.hbdb.hb_info
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.map.hbdb.hdb
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.map.hbdb.sig
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.map.hdb
AD_1/incremental_db/compiled_partitions/AD_1.root_partition.map.kpt
AD_1/incremental_db/README
AD_1/LED.v
AD_1/LED.v.bak
AD_1/simulation/modelsim/AD_1.sft
AD_1/simulation/modelsim/AD_1.vo
AD_1/simulation/modelsim/AD_1_fast.vo
AD_1/simulation/modelsim/AD_1_modelsim.xrf
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do.bak
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do.bak1
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do.bak10
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do.bak11
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do.bak2
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do.bak3
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do.bak4
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do.bak5
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do.bak6
AD_1/simulation/modelsim/AD_1_run_msim_rtl_verilog.do.bak

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