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文件名称:FPGA-LCD

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [MacOS] [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    16.67mb
  • 已下载：
    1次
  • 提 供 者：
    付***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

利用FPGA，结合NIOS方案，驱动TFT4.3寸屏并显示。-Use of FPGA, combined with NIOS scheme, drive TFT4.3 inch screen and display.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA LCD/
FPGA LCD/.sopc_builder/
FPGA LCD/.sopc_builder/filters.xml
FPGA LCD/.sopc_builder/install.ptf
FPGA LCD/.sopc_builder/install2.ptf
FPGA LCD/.sopc_builder/preferences.xml
FPGA LCD/cpu_0.ocp
FPGA LCD/cpu_0.sdc
FPGA LCD/cpu_0.v
FPGA LCD/cpu_0_bht_ram.mif
FPGA LCD/cpu_0_dc_tag_ram.mif
FPGA LCD/cpu_0_ic_tag_ram.mif
FPGA LCD/cpu_0_jtag_debug_module_sysclk.v
FPGA LCD/cpu_0_jtag_debug_module_tck.v
FPGA LCD/cpu_0_jtag_debug_module_wrapper.v
FPGA LCD/cpu_0_mult_cell.v
FPGA LCD/cpu_0_ociram_default_contents.mif
FPGA LCD/cpu_0_oci_test_bench.v
FPGA LCD/cpu_0_rf_ram_a.mif
FPGA LCD/cpu_0_rf_ram_b.mif
FPGA LCD/cpu_0_test_bench.v
FPGA LCD/db/
FPGA LCD/db/altsyncram_05p3.tdf
FPGA LCD/db/altsyncram_29f1.tdf
FPGA LCD/db/altsyncram_2ef1.tdf
FPGA LCD/db/altsyncram_87f1.tdf
FPGA LCD/db/altsyncram_8eq1.tdf
FPGA LCD/db/altsyncram_8pf1.tdf
FPGA LCD/db/altsyncram_97f1.tdf
FPGA LCD/db/altsyncram_9vc1.tdf
FPGA LCD/db/altsyncram_c572.tdf
FPGA LCD/db/altsyncram_ceq1.tdf
FPGA LCD/db/altsyncram_d5g1.tdf
FPGA LCD/db/altsyncram_e502.tdf
FPGA LCD/db/altsyncram_hg41.tdf
FPGA LCD/db/altsyncram_ntd1.tdf
FPGA LCD/db/altsyncram_oej1.tdf
FPGA LCD/db/altsyncram_qed1.tdf
FPGA LCD/db/altsyncram_s4p3.tdf
FPGA LCD/db/altsyncram_ttd1.tdf
FPGA LCD/db/a_dpfifo_5h21.tdf
FPGA LCD/db/a_dpfifo_8h21.tdf
FPGA LCD/db/cmpr_2o8.tdf
FPGA LCD/db/cmpr_3o8.tdf
FPGA LCD/db/cmpr_5cc.tdf
FPGA LCD/db/cmpr_9cc.tdf
FPGA LCD/db/cmpr_acc.tdf
FPGA LCD/db/cntr_2ci.tdf
FPGA LCD/db/cntr_32j.tdf
FPGA LCD/db/cntr_d5b.tdf
FPGA LCD/db/cntr_e5b.tdf
FPGA LCD/db/cntr_f5b.tdf
FPGA LCD/db/cntr_gui.tdf
FPGA LCD/db/cntr_q57.tdf
FPGA LCD/db/cntr_r57.tdf
FPGA LCD/db/cntr_vbi.tdf
FPGA LCD/db/decode_rqf.tdf
FPGA LCD/db/ded_mult_2o81.tdf
FPGA LCD/db/dffpipe_93c.tdf
FPGA LCD/db/LCD_CTL.(0).cnf.cdb
FPGA LCD/db/LCD_CTL.(0).cnf.hdb
FPGA LCD/db/LCD_CTL.(1).cnf.cdb
FPGA LCD/db/LCD_CTL.(1).cnf.hdb
FPGA LCD/db/LCD_CTL.(10).cnf.cdb
FPGA LCD/db/LCD_CTL.(10).cnf.hdb
FPGA LCD/db/LCD_CTL.(100).cnf.cdb
FPGA LCD/db/LCD_CTL.(100).cnf.hdb
FPGA LCD/db/LCD_CTL.(101).cnf.cdb
FPGA LCD/db/LCD_CTL.(101).cnf.hdb
FPGA LCD/db/LCD_CTL.(102).cnf.cdb
FPGA LCD/db/LCD_CTL.(102).cnf.hdb
FPGA LCD/db/LCD_CTL.(103).cnf.cdb
FPGA LCD/db/LCD_CTL.(103).cnf.hdb
FPGA LCD/db/LCD_CTL.(104).cnf.cdb
FPGA LCD/db/LCD_CTL.(104).cnf.hdb
FPGA LCD/db/LCD_CTL.(105).cnf.cdb
FPGA LCD/db/LCD_CTL.(105).cnf.hdb
FPGA LCD/db/LCD_CTL.(106).cnf.cdb
FPGA LCD/db/LCD_CTL.(106).cnf.hdb
FPGA LCD/db/LCD_CTL.(107).cnf.cdb
FPGA LCD/db/LCD_CTL.(107).cnf.hdb
FPGA LCD/db/LCD_CTL.(108).cnf.cdb
FPGA LCD/db/LCD_CTL.(108).cnf.hdb
FPGA LCD/db/LCD_CTL.(109).cnf.cdb
FPGA LCD/db/LCD_CTL.(109).cnf.hdb
FPGA LCD/db/LCD_CTL.(11).cnf.cdb
FPGA LCD/db/LCD_CTL.(11).cnf.hdb
FPGA LCD/db/LCD_CTL.(110).cnf.cdb
FPGA LCD/db/LCD_CTL.(110).cnf.hdb
FPGA LCD/db/LCD_CTL.(111).cnf.cdb
FPGA LCD/db/LCD_CTL.(111).cnf.hdb
FPGA LCD/db/LCD_CTL.(112).cnf.cdb
FPGA LCD/db/LCD_CTL.(112).cnf.hdb
FPGA LCD/db/LCD_CTL.(113).cnf.cdb
FPGA LCD/db/LCD_CTL.(113).cnf.hdb
FPGA LCD/db/LCD_CTL.(114).cnf.cdb
FPGA LCD/db/LCD_CTL.(114).cnf.hdb
FPGA LCD/db/LCD_CTL.(115).cnf.cdb
FPGA LCD/db/LCD_CTL.(115).cnf.hdb
FPGA LCD/db/LCD_CTL.(116).cnf.cdb
FPGA LCD/db/LCD_CTL.(116).cnf.hdb
FPGA LCD/db/LCD_CTL.(117).cnf.cdb
FPGA LCD/db/LCD_CTL.(117).cnf.hdb
FPGA LCD/db/LCD_CTL.(118).cnf.cdb
FPGA LCD/db/LCD_CTL.(118).cnf.hdb
FPGA LCD/db/LCD_CTL.(119).cnf.cdb
FPGA LCD/db/LCD_CTL.(119).cnf.hdb
FPGA LCD/db/LCD_CTL.(12).cnf.cdb
FPGA LCD/db/LCD_CTL.(12).cnf.hdb
FPGA LCD/db/LCD_CTL.(120).cnf.cdb
FPGA LCD/db/LCD_CTL.(120).cnf.hdb
FPGA LCD/db/LCD_CTL.(121).cnf.cdb
FPGA LCD/db/LCD_CTL.(121).cnf.hdb
FPGA LCD/db/LCD_CTL.(122).cnf.cdb
FPGA LCD/db/LCD_CTL.(122).cnf.hdb
FPGA LCD/db/LCD_CTL.(123).cnf.cdb
FPGA LCD/db/LCD_CTL.(123).cnf.hdb
FPGA LCD/db/LCD_CTL.(124).cnf.cdb
FPGA LCD/db/LCD_CTL.(124).cnf.hdb
FPGA LCD/db/LCD_CTL.(125).cnf.cdb
FPGA LCD/db/LCD_CTL.(125).cnf.hdb
FPGA LCD/db/LCD_CTL.(126).cnf.cdb
FPGA LCD/db/LCD_CTL.(126).cnf.hdb
FPGA LCD/db/LCD_CTL.(127).cnf.cdb
FPGA LCD/db/LCD_CTL.(127).cnf.hdb
FPGA LCD/db/LCD_CTL.(128).cnf.cdb
FPGA LCD/db/LCD_CTL.(128).cnf.hdb
FPGA LCD/db/LCD_CTL.(129).cnf.cdb
FPGA LCD/db/LCD_CTL.(129).cnf.hdb
FPGA LCD/db/LCD_CTL.(13).cnf.cdb
FPGA LCD/db/LCD_CTL.(13).cnf.hdb
FPGA LCD/db/LCD_CTL.(130).cnf.cdb
FPGA LCD/db/LCD_CTL.(130).cnf.hdb
FPGA LCD/db/LCD_CTL.(131).cnf.cdb
FPGA LCD/db/LCD_CTL.(131).cnf.hdb
FPGA LCD/db/LCD_CTL.(132).cnf.cdb
FPGA LCD/db/LCD_CTL.(132).cnf.hdb
FPGA LCD/db/LCD_CTL.(133).cnf.cdb
FPGA LCD/db/LCD_CTL.(133).cnf.hdb
FPGA LCD/db/LCD_CTL.(134).cnf.cdb
FPGA LCD/db/LCD_CTL.(134).cnf.hdb
FPGA LCD/db/LCD_CTL.(135).cnf.cdb
FPGA LCD/db/LCD_CTL.(135).cnf.hdb
FPGA LCD/db/LCD_CTL.(136).cnf.cdb
FPGA LCD/db/LCD_CTL.(136).cnf.hdb
FPGA LCD/db/LCD_CTL.(137).cnf.cdb
FPGA LCD/db/LCD_CTL.(137).cnf.hdb
FPGA LCD/db/LCD_CTL.(138).cnf.cdb
FPGA LCD/db/LCD_CTL.(138).cnf.hdb
FPGA LCD/db/LCD_CTL.(139).cnf.cdb
FPGA LCD/db/LCD_CTL.(139).cnf.hdb
FPGA LCD/db/LCD_CTL.(14).cnf.cdb
FPGA LCD/db/LCD_CTL.(14).cnf.hdb
FPGA LCD/db/LCD_CTL.(140).cnf.cdb
FPGA LCD/db/LCD_CTL.(140).cnf.hdb
FPGA LCD/db/LCD_CTL.(142).cnf.cdb
FPGA LCD/db/LCD_CTL.(142).cnf.hdb
FPGA LCD/db/LCD_CTL.(143).cnf.cdb
FPGA LCD/db/LCD_CTL.(143).cnf.hdb
FPGA LCD/db/LCD_CTL.(15

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