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文件名称:10-HDL-IP

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    195.36kb
  • 已下载：
    0次
  • 提 供 者：
    wangx******
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

alter公司开发板经典例程，其中主要内容是HDL-IP的例程，里面有串口、flash、以太网口设置初始化等等。-alter corporate development board classic routines, principal among which is the routine of HDL-IP, there are serial flash, Ethernet port setting initialization.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

10-HDL-IP/Verilog/ascii_bcd.v
10-HDL-IP/Verilog/bcd_ascii.v
10-HDL-IP/Verilog/buzz.v
10-HDL-IP/Verilog/clock.v
10-HDL-IP/Verilog/counter.v
10-HDL-IP/Verilog/counter_core.v
10-HDL-IP/Verilog/counter_sim.v
10-HDL-IP/Verilog/delay_time.v
10-HDL-IP/Verilog/divisor.v
10-HDL-IP/Verilog/div_sim.v
10-HDL-IP/Verilog/div_sim.v.bak
10-HDL-IP/Verilog/ds_drv.v
10-HDL-IP/Verilog/ds_drv_s.bdf
10-HDL-IP/Verilog/ds_drv_s.v
10-HDL-IP/Verilog/ds_sel.v
10-HDL-IP/Verilog/fifo.v
10-HDL-IP/Verilog/flash.v
10-HDL-IP/Verilog/i2c.v
10-HDL-IP/Verilog/io_tri_state.v
10-HDL-IP/Verilog/kb2bcd.v
10-HDL-IP/Verilog/kb_drv.v
10-HDL-IP/Verilog/kb_drv_test.v
10-HDL-IP/Verilog/key.v
10-HDL-IP/Verilog/lcd1602_drv.v
10-HDL-IP/Verilog/led_drv.v
10-HDL-IP/Verilog/mseq.v
10-HDL-IP/Verilog/msg_decode.v
10-HDL-IP/Verilog/msg_decode_test.v
10-HDL-IP/Verilog/msg_encode.v
10-HDL-IP/Verilog/mt48lc4m32b2.v
10-HDL-IP/Verilog/mt48lc4m32b2_test.v
10-HDL-IP/Verilog/ps2_drv.v
10-HDL-IP/Verilog/pwm.v
10-HDL-IP/Verilog/pwm_counter.v
10-HDL-IP/Verilog/s373.v
10-HDL-IP/Verilog/s373.v.bak
10-HDL-IP/Verilog/scan_ascii.v
10-HDL-IP/Verilog/sdram.v
10-HDL-IP/Verilog/sdram.v.bak
10-HDL-IP/Verilog/sel8.v
10-HDL-IP/Verilog/shifter.v
10-HDL-IP/Verilog/spi.v
10-HDL-IP/Verilog/timer.v
10-HDL-IP/Verilog/uart_rx.v
10-HDL-IP/Verilog/uart_tx.v
10-HDL-IP/Verilog/usb.v
10-HDL-IP/Verilog/vga_drv.v
10-HDL-IP/Verilog/复件 sdram.v
10-HDL-IP/Verilog.rar
10-HDL-IP/VHDL/am29lv320d.vhd
10-HDL-IP/VHDL/ascii_bcd.vhd
10-HDL-IP/VHDL/bcd_ascii.vhd
10-HDL-IP/VHDL/buzz.vhd
10-HDL-IP/VHDL/charlib8_8.vhd
10-HDL-IP/VHDL/clock.vhd
10-HDL-IP/VHDL/counter.vhd
10-HDL-IP/VHDL/counter_sim.vhd
10-HDL-IP/VHDL/CY7C68013A.vhd
10-HDL-IP/VHDL/delay_time.vhd
10-HDL-IP/VHDL/diff.vhd
10-HDL-IP/VHDL/divisor.vhd
10-HDL-IP/VHDL/div_sim.vhd
10-HDL-IP/VHDL/ds_drv.vhd
10-HDL-IP/VHDL/ds_drv_s.bdf
10-HDL-IP/VHDL/ds_drv_s.vhd.bak
10-HDL-IP/VHDL/ds_sel.vhd
10-HDL-IP/VHDL/fifo_def.vhd
10-HDL-IP/VHDL/flash.vhd
10-HDL-IP/VHDL/flash_test.vhd
10-HDL-IP/VHDL/i2c.vhd
10-HDL-IP/VHDL/i2c_dev.vhd
10-HDL-IP/VHDL/i2c_test.vhd
10-HDL-IP/VHDL/io_tri_state.vhd
10-HDL-IP/VHDL/kb2bcd.vhd
10-HDL-IP/VHDL/kb_dev.vhd
10-HDL-IP/VHDL/kb_drv.vhd
10-HDL-IP/VHDL/lcd1602_drv.vhd
10-HDL-IP/VHDL/ledarray_drv.vhd
10-HDL-IP/VHDL/led_drv.vhd
10-HDL-IP/VHDL/mseq.vhd
10-HDL-IP/VHDL/msg_decode.vhd
10-HDL-IP/VHDL/msg_decode_test.vhd
10-HDL-IP/VHDL/msg_encode.vhd
10-HDL-IP/VHDL/msg_encode_test.vhd
10-HDL-IP/VHDL/ps2_drv.vhd
10-HDL-IP/VHDL/ps2_drv_test.vhd
10-HDL-IP/VHDL/pwm.vhd
10-HDL-IP/VHDL/pwm_counter.vhd
10-HDL-IP/VHDL/s373.vhd
10-HDL-IP/VHDL/scan_ascii.vhd
10-HDL-IP/VHDL/sdram.vhd
10-HDL-IP/VHDL/sdram_test.vhd
10-HDL-IP/VHDL/sel8.vhd
10-HDL-IP/VHDL/shifter.vhd
10-HDL-IP/VHDL/shifter_test.vhd
10-HDL-IP/VHDL/spi.vhd
10-HDL-IP/VHDL/spi_test.vhd
10-HDL-IP/VHDL/spi_test_dev.vhd
10-HDL-IP/VHDL/timer.vhd
10-HDL-IP/VHDL/uart_rx.vhd
10-HDL-IP/VHDL/uart_rx_test.vhd
10-HDL-IP/VHDL/uart_tx.vhd
10-HDL-IP/VHDL/uart_tx_test.vhd
10-HDL-IP/VHDL/usb.vhd
10-HDL-IP/VHDL/vga_drv.vhd
10-HDL-IP/Verilog
10-HDL-IP/VHDL
10-HDL-IP

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