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文件名称:simple_clock

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.72mb
  • 已下载：
    0次
  • 提 供 者：
  • 相关连接：
    无
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修正介绍说明

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基于ｆｐｇａ的简单时钟，可以作为本科课程设计的内容，用ｖｅｒｉｌｏｇ编写的-Fpga-based simple clock, as the content of the undergraduate curriculum design with verilog prepared
(系统自动生成,下载前可以参看下载内容)

下载文件列表

simple_clock/
simple_clock/simple_clock/
simple_clock/simple_clock/db/
simple_clock/simple_clock/db/main_test.(0).cnf.cdb
simple_clock/simple_clock/db/main_test.(0).cnf.hdb
simple_clock/simple_clock/db/main_test.(1).cnf.cdb
simple_clock/simple_clock/db/main_test.(1).cnf.hdb
simple_clock/simple_clock/db/main_test.(10).cnf.cdb
simple_clock/simple_clock/db/main_test.(10).cnf.hdb
simple_clock/simple_clock/db/main_test.(2).cnf.cdb
simple_clock/simple_clock/db/main_test.(2).cnf.hdb
simple_clock/simple_clock/db/main_test.(3).cnf.cdb
simple_clock/simple_clock/db/main_test.(3).cnf.hdb
simple_clock/simple_clock/db/main_test.(4).cnf.cdb
simple_clock/simple_clock/db/main_test.(4).cnf.hdb
simple_clock/simple_clock/db/main_test.(5).cnf.cdb
simple_clock/simple_clock/db/main_test.(5).cnf.hdb
simple_clock/simple_clock/db/main_test.(6).cnf.cdb
simple_clock/simple_clock/db/main_test.(6).cnf.hdb
simple_clock/simple_clock/db/main_test.(7).cnf.cdb
simple_clock/simple_clock/db/main_test.(7).cnf.hdb
simple_clock/simple_clock/db/main_test.(8).cnf.cdb
simple_clock/simple_clock/db/main_test.(8).cnf.hdb
simple_clock/simple_clock/db/main_test.(9).cnf.cdb
simple_clock/simple_clock/db/main_test.(9).cnf.hdb
simple_clock/simple_clock/db/main_test.ae.hdb
simple_clock/simple_clock/db/main_test.cbx.xml
simple_clock/simple_clock/db/main_test.cmp.rdb
simple_clock/simple_clock/db/main_test.db_info
simple_clock/simple_clock/db/main_test.eco.cdb
simple_clock/simple_clock/db/main_test.hier_info
simple_clock/simple_clock/db/main_test.hif
simple_clock/simple_clock/db/main_test.lpc.html
simple_clock/simple_clock/db/main_test.lpc.rdb
simple_clock/simple_clock/db/main_test.lpc.txt
simple_clock/simple_clock/db/main_test.map.qmsg
simple_clock/simple_clock/db/main_test.pre_map.cdb
simple_clock/simple_clock/db/main_test.pre_map.hdb
simple_clock/simple_clock/db/main_test.rtlv.hdb
simple_clock/simple_clock/db/main_test.rtlv_sg.cdb
simple_clock/simple_clock/db/main_test.rtlv_sg_swap.cdb
simple_clock/simple_clock/db/main_test.sld_design_entry.sci
simple_clock/simple_clock/db/main_test.sld_design_entry_dsc.sci
simple_clock/simple_clock/db/main_test.sta.qmsg
simple_clock/simple_clock/db/main_test.tan.qmsg
simple_clock/simple_clock/db/main_test.tmw_info
simple_clock/simple_clock/db/prev_cmp_main_test.map.qmsg
simple_clock/simple_clock/db/prev_cmp_main_test.qmsg
simple_clock/simple_clock/incremental_db/
simple_clock/simple_clock/incremental_db/compiled_partitions/
simple_clock/simple_clock/incremental_db/README
simple_clock/simple_clock/main_test.done
simple_clock/simple_clock/main_test.flow.rpt
simple_clock/simple_clock/main_test.map.rpt
simple_clock/simple_clock/main_test.map.summary
simple_clock/simple_clock/main_test.qpf
simple_clock/simple_clock/main_test.qsf
simple_clock/simple_clock/main_test.qws
simple_clock/simple_clock/src/
simple_clock/simple_clock/src/control.vhd
simple_clock/simple_clock/src/controlen.vhd
simple_clock/simple_clock/src/counter.vhd
simple_clock/simple_clock/src/count_10.vhd
simple_clock/simple_clock/src/count_10_6_10_10.vhd
simple_clock/simple_clock/src/count_6.vhd
simple_clock/simple_clock/src/decoder.vhd
simple_clock/simple_clock/src/display.vhd
simple_clock/simple_clock/src/fen_pin.vhd
simple_clock/simple_clock/src/main_control.vhd
simple_clock/simple_clock/src/main_test.vhd
simple_clock/simple_clock_modelsim/
simple_clock/simple_clock_modelsim/rsc/
simple_clock/simple_clock_modelsim/rsc/clock_counter.v
simple_clock/simple_clock_modelsim/rsc/clock_set.v
simple_clock/simple_clock_modelsim/rsc/clock_top.v
simple_clock/simple_clock_modelsim/rsc/counter_6.v
simple_clock/simple_clock_modelsim/rsc/decoder3_8.v
simple_clock/simple_clock_modelsim/rsc/hour_decoder.v
simple_clock/simple_clock_modelsim/rsc/led_display.v
simple_clock/simple_clock_modelsim/rsc/led_display.v.bak
simple_clock/simple_clock_modelsim/rsc/mux6_1.v
simple_clock/simple_clock_modelsim/rsc/mux6_1.v.bak
simple_clock/simple_clock_modelsim/rsc/nomal_decoder.v
simple_clock/simple_clock_modelsim/simple_clock_modelsim.cr.mti
simple_clock/simple_clock_modelsim/simple_clock_modelsim.mpf
simple_clock/simple_clock_modelsim/work/
simple_clock/simple_clock_modelsim/work/clock_counter/
simple_clock/simple_clock_modelsim/work/clock_counter/_primary.dat
simple_clock/simple_clock_modelsim/work/clock_counter/_primary.dbs
simple_clock/simple_clock_modelsim/work/clock_counter/_primary.vhd
simple_clock/simple_clock_modelsim/work/clock_set/
simple_clock/simple_clock_modelsim/work/clock_set/_primary.dat
simple_clock/simple_clock_modelsim/work/clock_set/_primary.dbs
simple_clock/simple_clock_modelsim/work/clock_set/_primary.vhd
simple_clock/simple_clock_modelsim/work/clock_top/
simple_clock/simple_clock_modelsim/work/clock_top/_primary.dat
simple_clock/simple_clock_modelsim/work/clock_top/_primary.dbs
simple_clock/simple_clock_modelsim/work/clock_top/_primary.vhd
simple_clock/simple_clock_modelsim/work/counter_6/
simple_clock/simple_clock_modelsim/work/counter_6/_primary.dat
simple_clock/simple_clock_modelsim/work/counter_6/_primary.dbs
simple_clock/simple_clock_modelsim/work/counter_6/_primary.vhd
simple_clock/si

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