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文件名称:Flash-Memory-RAM

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-03-08
  • 文件大小：
    14.39mb
  • 已下载：
    0次
  • 提 供 者：
    x****
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

周立功Fusion StartKit，fpga开发板的实验例程，Flash Memory初始化RAM实验-ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Flash Memory初始化RAM实验/Project/component/PLL_1M.edn
Flash Memory初始化RAM实验/Project/component/work/asf/asf.sdb
Flash Memory初始化RAM实验/Project/constraint/FlashinitialRAM.pdc
Flash Memory初始化RAM实验/Project/constraint/Flash_intial_RAM_main.pdc
Flash Memory初始化RAM实验/Project/constraint/main_sdc.sdc
Flash Memory初始化RAM实验/Project/coreconsole/dfh/dfh.cci
Flash Memory初始化RAM实验/Project/coreconsole/dfh/dfh.cco
Flash Memory初始化RAM实验/Project/coreconsole/dfh/dfh.xml
Flash Memory初始化RAM实验/Project/coreconsole/wyq/wyq.cci
Flash Memory初始化RAM实验/Project/coreconsole/wyq/wyq.xml
Flash Memory初始化RAM实验/Project/designer/impl1/designer.log
Flash Memory初始化RAM实验/Project/designer/impl1/designer_genhdl.log
Flash Memory初始化RAM实验/Project/designer/impl1/designer_gen_ba.log
Flash Memory初始化RAM实验/Project/designer/impl1/flash_initial.ide_des
Flash Memory初始化RAM实验/Project/designer/impl1/flash_initial.tcl
Flash Memory初始化RAM实验/Project/designer/impl1/main.adb
Flash Memory初始化RAM实验/Project/designer/impl1/main.dtf/verify.log
Flash Memory初始化RAM实验/Project/designer/impl1/main.ide_des
Flash Memory初始化RAM实验/Project/designer/impl1/main.pdb
Flash Memory初始化RAM实验/Project/designer/impl1/main.pdb.depends
Flash Memory初始化RAM实验/Project/designer/impl1/main.stp
Flash Memory初始化RAM实验/Project/designer/impl1/main.tcl
Flash Memory初始化RAM实验/Project/designer/impl1/main_ba.sdf
Flash Memory初始化RAM实验/Project/designer/impl1/main_ba.v
Flash Memory初始化RAM实验/Project/designer/impl1/my_ram.ide_des
Flash Memory初始化RAM实验/Project/designer/impl1/my_ram.tcl
Flash Memory初始化RAM实验/Project/designer/impl1/PLL_1M.ide_des
Flash Memory初始化RAM实验/Project/designer/impl1/PLL_1M.tcl
Flash Memory初始化RAM实验/Project/designer/impl1/send.tcl
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/main/verilog.psm
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/main/_primary.dat
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/main/_primary.vhd
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/stimulus/verilog.psm
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/stimulus/_primary.dat
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/stimulus/_primary.vhd
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/tb_clock_minmax/verilog.psm
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dat
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.vhd
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/testbench/verilog.psm
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/testbench/_primary.dat
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/testbench/_primary.vhd
Flash Memory初始化RAM实验/Project/designer/impl1/simulation/postlayout/_info
Flash Memory初始化RAM实验/Project/hdl/control_module.v
Flash Memory初始化RAM实验/Project/hdl/hdlsynchk.tcl
Flash Memory初始化RAM实验/Project/hdl/main.v
Flash Memory初始化RAM实验/Project/hdl/send.v
Flash Memory初始化RAM实验/Project/hdl/send_control.v
Flash Memory初始化RAM实验/Project/phy_synthesis/PLL_1M.edn
Flash Memory初始化RAM实验/Project/RAM_module.prj
Flash Memory初始化RAM实验/Project/simulation/flash_initial.mem
Flash Memory初始化RAM实验/Project/simulation/inilization.mem
Flash Memory初始化RAM实验/Project/simulation/modelsim.ini
Flash Memory初始化RAM实验/Project/simulation/modelsim.ini.sav
Flash Memory初始化RAM实验/Project/simulation/modelsim.log
Flash Memory初始化RAM实验/Project/simulation/my_initial_wyq.ahx
Flash Memory初始化RAM实验/Project/simulation/my_ram_block_0_my_ram_R0C0.mem
Flash Memory初始化RAM实验/Project/simulation/my_ram_R0C0.mem
Flash Memory初始化RAM实验/Project/simulation/newCore_acm_ram_R0C0.mem
Flash Memory初始化RAM实验/Project/simulation/newCore_assc_ram_R0C0.mem
Flash Memory初始化RAM实验/Project/simulation/newCore_smev_ram_R0C0.mem
Flash Memory初始化RAM实验/Project/simulation/newCore_smtr_ram_R0C0.mem
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@a_1s_1s/verilog.psm
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@a_1s_1s/_primary.dat
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@a_1s_1s/_primary.vhd
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@a_1s_1s_1s/verilog.psm
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@a_1s_1s_1s/_primary.dat
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@a_1s_1s_1s/_primary.vhd
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@b_1s_1s/verilog.psm
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@b_1s_1s/_primary.dat
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@b_1s_1s/_primary.vhd
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@b_1s_1s_1s/verilog.psm
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@b_1s_1s_1s/_primary.dat
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@b_1s_1s_1s/_primary.vhd
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@c_1s_1s_9s/verilog.psm
Flash Memory初始化RAM实验/Project/simulation/postsynth/@i@n@i@t@c@f@g_@x@c_1s_1s_9s/_primary.dat
Flash Memory初始化RAM实验/P

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