文件名称:lcd_verilog
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- 上传时间:2013-04-13
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文件大小:442.9kb
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LCD显示模块的编码,可以FPGA的LCD显示屏上显示文字-LCD display module coding FPGA LCD screen to display text
(系统自动生成,下载前可以参看下载内容)
下载文件列表
lcd_verilog/counter.v
lcd_verilog/DCM_66Mhz.v
lcd_verilog/DCM_66Mhz_arwz.ucf
lcd_verilog/iseconfig/lcd_top.xreport
lcd_verilog/iseconfig/lcd_verilog.projectmgr
lcd_verilog/lcd_bus_mux.v
lcd_verilog/lcd_ctrl.v
lcd_verilog/lcd_init.v
lcd_verilog/lcd_top.bgn
lcd_verilog/lcd_top.bit
lcd_verilog/lcd_top.bld
lcd_verilog/lcd_top.cmd_log
lcd_verilog/lcd_top.drc
lcd_verilog/lcd_top.lso
lcd_verilog/lcd_top.ncd
lcd_verilog/lcd_top.ngc
lcd_verilog/lcd_top.ngd
lcd_verilog/lcd_top.ngr
lcd_verilog/lcd_top.pad
lcd_verilog/lcd_top.par
lcd_verilog/lcd_top.pcf
lcd_verilog/lcd_top.prj
lcd_verilog/lcd_top.ptwx
lcd_verilog/lcd_top.stx
lcd_verilog/lcd_top.syr
lcd_verilog/lcd_top.twr
lcd_verilog/lcd_top.twx
lcd_verilog/lcd_top.ucf
lcd_verilog/lcd_top.unroutes
lcd_verilog/lcd_top.ut
lcd_verilog/lcd_top.v
lcd_verilog/lcd_top.xpi
lcd_verilog/lcd_top.xst
lcd_verilog/lcd_top_bitgen.xwbt
lcd_verilog/lcd_top_envsettings.html
lcd_verilog/lcd_top_guide.ncd
lcd_verilog/lcd_top_map.map
lcd_verilog/lcd_top_map.mrp
lcd_verilog/lcd_top_map.ncd
lcd_verilog/lcd_top_map.ngm
lcd_verilog/lcd_top_map.xrpt
lcd_verilog/lcd_top_ngdbuild.xrpt
lcd_verilog/lcd_top_pad.csv
lcd_verilog/lcd_top_pad.txt
lcd_verilog/lcd_top_par.xrpt
lcd_verilog/lcd_top_summary.html
lcd_verilog/lcd_top_summary.xml
lcd_verilog/lcd_top_usage.xml
lcd_verilog/lcd_top_xst.xrpt
lcd_verilog/lcd_verilog.gise
lcd_verilog/lcd_verilog.xise
lcd_verilog/usage_statistics_webtalk.html
lcd_verilog/webtalk.log
lcd_verilog/webtalk_pn.xml
lcd_verilog/xaw2verilog.log
lcd_verilog/xlnx_auto_0_xdb/cst.xbcd
lcd_verilog/xst/work/hdllib.ref
lcd_verilog/xst/work/hdpdeps.ref
lcd_verilog/xst/work/sub00/vhpl00.vho
lcd_verilog/xst/work/sub00/vhpl01.vho
lcd_verilog/xst/work/sub00/vhpl02.vho
lcd_verilog/xst/work/sub00/vhpl03.vho
lcd_verilog/xst/work/sub00/vhpl04.vho
lcd_verilog/xst/work/vlg10/counter.bin
lcd_verilog/xst/work/vlg1E/lcd__init.bin
lcd_verilog/xst/work/vlg26/_d_c_m__66_mhz.bin
lcd_verilog/xst/work/vlg41/lcd__top.bin
lcd_verilog/xst/work/vlg69/lcd__bus__mux.bin
lcd_verilog/xst/work/vlg6B/lcd__ctrl.bin
lcd_verilog/_ngo/netlist.lst
lcd_verilog/_xmsgs/bitgen.xmsgs
lcd_verilog/_xmsgs/map.xmsgs
lcd_verilog/_xmsgs/ngdbuild.xmsgs
lcd_verilog/_xmsgs/par.xmsgs
lcd_verilog/_xmsgs/pn_parser.xmsgs
lcd_verilog/_xmsgs/trce.xmsgs
lcd_verilog/_xmsgs/xst.xmsgs
lcd_verilog/xst/dump.xst/lcd_top.prj/ngx/notopt
lcd_verilog/xst/dump.xst/lcd_top.prj/ngx/opt
lcd_verilog/xst/dump.xst/lcd_top.prj/ngx
lcd_verilog/xst/dump.xst/lcd_top.prj
lcd_verilog/xst/work/sub00
lcd_verilog/xst/work/vlg10
lcd_verilog/xst/work/vlg1E
lcd_verilog/xst/work/vlg26
lcd_verilog/xst/work/vlg41
lcd_verilog/xst/work/vlg69
lcd_verilog/xst/work/vlg6B
lcd_verilog/xst/dump.xst
lcd_verilog/xst/file graph
lcd_verilog/xst/projnav.tmp
lcd_verilog/xst/work
lcd_verilog/iseconfig
lcd_verilog/xlnx_auto_0_xdb
lcd_verilog/xst
lcd_verilog/_ngo
lcd_verilog/_xmsgs
lcd_verilog
lcd_verilog/DCM_66Mhz.v
lcd_verilog/DCM_66Mhz_arwz.ucf
lcd_verilog/iseconfig/lcd_top.xreport
lcd_verilog/iseconfig/lcd_verilog.projectmgr
lcd_verilog/lcd_bus_mux.v
lcd_verilog/lcd_ctrl.v
lcd_verilog/lcd_init.v
lcd_verilog/lcd_top.bgn
lcd_verilog/lcd_top.bit
lcd_verilog/lcd_top.bld
lcd_verilog/lcd_top.cmd_log
lcd_verilog/lcd_top.drc
lcd_verilog/lcd_top.lso
lcd_verilog/lcd_top.ncd
lcd_verilog/lcd_top.ngc
lcd_verilog/lcd_top.ngd
lcd_verilog/lcd_top.ngr
lcd_verilog/lcd_top.pad
lcd_verilog/lcd_top.par
lcd_verilog/lcd_top.pcf
lcd_verilog/lcd_top.prj
lcd_verilog/lcd_top.ptwx
lcd_verilog/lcd_top.stx
lcd_verilog/lcd_top.syr
lcd_verilog/lcd_top.twr
lcd_verilog/lcd_top.twx
lcd_verilog/lcd_top.ucf
lcd_verilog/lcd_top.unroutes
lcd_verilog/lcd_top.ut
lcd_verilog/lcd_top.v
lcd_verilog/lcd_top.xpi
lcd_verilog/lcd_top.xst
lcd_verilog/lcd_top_bitgen.xwbt
lcd_verilog/lcd_top_envsettings.html
lcd_verilog/lcd_top_guide.ncd
lcd_verilog/lcd_top_map.map
lcd_verilog/lcd_top_map.mrp
lcd_verilog/lcd_top_map.ncd
lcd_verilog/lcd_top_map.ngm
lcd_verilog/lcd_top_map.xrpt
lcd_verilog/lcd_top_ngdbuild.xrpt
lcd_verilog/lcd_top_pad.csv
lcd_verilog/lcd_top_pad.txt
lcd_verilog/lcd_top_par.xrpt
lcd_verilog/lcd_top_summary.html
lcd_verilog/lcd_top_summary.xml
lcd_verilog/lcd_top_usage.xml
lcd_verilog/lcd_top_xst.xrpt
lcd_verilog/lcd_verilog.gise
lcd_verilog/lcd_verilog.xise
lcd_verilog/usage_statistics_webtalk.html
lcd_verilog/webtalk.log
lcd_verilog/webtalk_pn.xml
lcd_verilog/xaw2verilog.log
lcd_verilog/xlnx_auto_0_xdb/cst.xbcd
lcd_verilog/xst/work/hdllib.ref
lcd_verilog/xst/work/hdpdeps.ref
lcd_verilog/xst/work/sub00/vhpl00.vho
lcd_verilog/xst/work/sub00/vhpl01.vho
lcd_verilog/xst/work/sub00/vhpl02.vho
lcd_verilog/xst/work/sub00/vhpl03.vho
lcd_verilog/xst/work/sub00/vhpl04.vho
lcd_verilog/xst/work/vlg10/counter.bin
lcd_verilog/xst/work/vlg1E/lcd__init.bin
lcd_verilog/xst/work/vlg26/_d_c_m__66_mhz.bin
lcd_verilog/xst/work/vlg41/lcd__top.bin
lcd_verilog/xst/work/vlg69/lcd__bus__mux.bin
lcd_verilog/xst/work/vlg6B/lcd__ctrl.bin
lcd_verilog/_ngo/netlist.lst
lcd_verilog/_xmsgs/bitgen.xmsgs
lcd_verilog/_xmsgs/map.xmsgs
lcd_verilog/_xmsgs/ngdbuild.xmsgs
lcd_verilog/_xmsgs/par.xmsgs
lcd_verilog/_xmsgs/pn_parser.xmsgs
lcd_verilog/_xmsgs/trce.xmsgs
lcd_verilog/_xmsgs/xst.xmsgs
lcd_verilog/xst/dump.xst/lcd_top.prj/ngx/notopt
lcd_verilog/xst/dump.xst/lcd_top.prj/ngx/opt
lcd_verilog/xst/dump.xst/lcd_top.prj/ngx
lcd_verilog/xst/dump.xst/lcd_top.prj
lcd_verilog/xst/work/sub00
lcd_verilog/xst/work/vlg10
lcd_verilog/xst/work/vlg1E
lcd_verilog/xst/work/vlg26
lcd_verilog/xst/work/vlg41
lcd_verilog/xst/work/vlg69
lcd_verilog/xst/work/vlg6B
lcd_verilog/xst/dump.xst
lcd_verilog/xst/file graph
lcd_verilog/xst/projnav.tmp
lcd_verilog/xst/work
lcd_verilog/iseconfig
lcd_verilog/xlnx_auto_0_xdb
lcd_verilog/xst
lcd_verilog/_ngo
lcd_verilog/_xmsgs
lcd_verilog
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