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文件名称:uart_Verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-04-23
  • 文件大小：
    4.6mb
  • 已下载：
    0次
  • 提 供 者：
    xuxin*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于Verilog的RS232串口通信实验，可发送256位数据，并在Altera的EP4CE15F17C8芯片上验证成功。-Verilog-based RS232 serial communication experiment, 256-bit data can be sent on Altera' s EP4CE15F17C8 chip authentication is successful.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart_lab6/db/logic_util_heursitic.dat
uart_lab6/db/prev_cmp_uart_lab6.qmsg
uart_lab6/db/uart_lab6.(0).cnf.cdb
uart_lab6/db/uart_lab6.(0).cnf.hdb
uart_lab6/db/uart_lab6.(1).cnf.cdb
uart_lab6/db/uart_lab6.(1).cnf.hdb
uart_lab6/db/uart_lab6.(2).cnf.cdb
uart_lab6/db/uart_lab6.(2).cnf.hdb
uart_lab6/db/uart_lab6.amm.cdb
uart_lab6/db/uart_lab6.asm.qmsg
uart_lab6/db/uart_lab6.asm.rdb
uart_lab6/db/uart_lab6.asm_labs.ddb
uart_lab6/db/uart_lab6.cbx.xml
uart_lab6/db/uart_lab6.cmp.bpm
uart_lab6/db/uart_lab6.cmp.cdb
uart_lab6/db/uart_lab6.cmp.hdb
uart_lab6/db/uart_lab6.cmp.kpt
uart_lab6/db/uart_lab6.cmp.logdb
uart_lab6/db/uart_lab6.cmp.rdb
uart_lab6/db/uart_lab6.cmp_merge.kpt
uart_lab6/db/uart_lab6.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
uart_lab6/db/uart_lab6.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
uart_lab6/db/uart_lab6.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
uart_lab6/db/uart_lab6.db_info
uart_lab6/db/uart_lab6.eda.qmsg
uart_lab6/db/uart_lab6.fit.qmsg
uart_lab6/db/uart_lab6.hier_info
uart_lab6/db/uart_lab6.hif
uart_lab6/db/uart_lab6.idb.cdb
uart_lab6/db/uart_lab6.lpc.html
uart_lab6/db/uart_lab6.lpc.rdb
uart_lab6/db/uart_lab6.lpc.txt
uart_lab6/db/uart_lab6.map.bpm
uart_lab6/db/uart_lab6.map.cdb
uart_lab6/db/uart_lab6.map.hdb
uart_lab6/db/uart_lab6.map.kpt
uart_lab6/db/uart_lab6.map.logdb
uart_lab6/db/uart_lab6.map.qmsg
uart_lab6/db/uart_lab6.map_bb.cdb
uart_lab6/db/uart_lab6.map_bb.hdb
uart_lab6/db/uart_lab6.map_bb.logdb
uart_lab6/db/uart_lab6.pre_map.cdb
uart_lab6/db/uart_lab6.pre_map.hdb
uart_lab6/db/uart_lab6.rtlv.hdb
uart_lab6/db/uart_lab6.rtlv_sg.cdb
uart_lab6/db/uart_lab6.rtlv_sg_swap.cdb
uart_lab6/db/uart_lab6.sgdiff.cdb
uart_lab6/db/uart_lab6.sgdiff.hdb
uart_lab6/db/uart_lab6.sld_design_entry.sci
uart_lab6/db/uart_lab6.sld_design_entry_dsc.sci
uart_lab6/db/uart_lab6.smart_action.txt
uart_lab6/db/uart_lab6.sta.qmsg
uart_lab6/db/uart_lab6.sta.rdb
uart_lab6/db/uart_lab6.sta_cmp.8_slow_1200mv_85c.tdb
uart_lab6/db/uart_lab6.syn_hier_info
uart_lab6/db/uart_lab6.tiscmp.fastest_slow_1200mv_0c.ddb
uart_lab6/db/uart_lab6.tiscmp.fastest_slow_1200mv_85c.ddb
uart_lab6/db/uart_lab6.tiscmp.fast_1200mv_0c.ddb
uart_lab6/db/uart_lab6.tiscmp.slow_1200mv_0c.ddb
uart_lab6/db/uart_lab6.tiscmp.slow_1200mv_85c.ddb
uart_lab6/db/uart_lab6.tis_db_list.ddb
uart_lab6/db/uart_lab6.tmw_info
uart_lab6/incremental_db/compiled_partitions/uart_lab6.db_info
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.cmp.cdb
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.cmp.dfp
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.cmp.hdb
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.cmp.kpt
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.cmp.logdb
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.cmp.rcfdb
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.map.cdb
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.map.dpi
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.map.hbdb.cdb
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.map.hbdb.hb_info
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.map.hbdb.hdb
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.map.hbdb.sig
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.map.hdb
uart_lab6/incremental_db/compiled_partitions/uart_lab6.root_partition.map.kpt
uart_lab6/incremental_db/README
uart_lab6/simulation/modelsim/uart_lab6.sft
uart_lab6/simulation/modelsim/uart_lab6.vo
uart_lab6/simulation/modelsim/uart_lab6_8_1200mv_0c_slow.vo
uart_lab6/simulation/modelsim/uart_lab6_8_1200mv_0c_v_slow.sdo
uart_lab6/simulation/modelsim/uart_lab6_8_1200mv_85c_slow.vo
uart_lab6/simulation/modelsim/uart_lab6_8_1200mv_85c_v_slow.sdo
uart_lab6/simulation/modelsim/uart_lab6_min_1200mv_0c_fast.vo
uart_lab6/simulation/modelsim/uart_lab6_min_1200mv_0c_v_fast.sdo
uart_lab6/simulation/modelsim/uart_lab6_modelsim.xrf
uart_lab6/simulation/modelsim/uart_lab6_v.sdo
uart_lab6/uart_lab6.asm.rpt
uart_lab6/uart_lab6.cdf
uart_lab6/uart_lab6.done
uart_lab6/uart_lab6.eda.rpt
uart_lab6/uart_lab6.fit.rpt
uart_lab6/uart_lab6.fit.smsg
uart_lab6/uart_lab6.fit.summary
uart_lab6/uart_lab6.flow.rpt
uart_lab6/uart_lab6.map.rpt
uart_lab6/uart_lab6.map.summary
uart_lab6/uart_lab6.pin
uart_lab6/uart_lab6.qpf
uart_lab6/uart_lab6.qsf
uart_lab6/uart_lab6.sof
uart_lab6/uart_lab6.sta.rpt
uart_lab6/uart_lab6.sta.summary
uart_lab6/uart_rxd.v
uart_lab6/uart_rxd.v.bak
uart_lab6/uart_top.v
uart_lab6/uart_top.v.bak
uart_lab6/uart_txd.v
uart_lab6/uart_txd.v.bak
uart_lab6/incremental_db/compiled_partitions
uart_lab6/simulation/modelsim
uart_lab6/db
uart_lab6/incremental_db
uart_lab6/simulation
uart_lab6

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