./README.txt
./README_Apache_License.txt
./README_GNU_LGPL_License.txt
./README_terms_and_conditions.txt
./designs/
./designs/socv/
./designs/socv/rtl/
./designs/socv/rtl/rtl_lpw/
./designs/socv/rtl/rtl_lpw/ahb2apb/
./designs/socv/rtl/rtl_lpw/ahb2apb/rtl/
./designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb.f
./designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb.irunargs
./designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb.v
./designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb_bug.irunargs
./designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb_lab1.v
./designs/socv/rtl/rtl_lpw/ahb2apb/rtl/ahb2apb_defines.v
./designs/socv/rtl/rtl_lpw/alut/
./designs/socv/rtl/rtl_lpw/alut/rtl/
./designs/socv/rtl/rtl_lpw/alut/rtl/alut.irunargs
./designs/socv/rtl/rtl_lpw/alut/rtl/alut.v
./designs/socv/rtl/rtl_lpw/alut/rtl/alut_addr_checker.v
./designs/socv/rtl/rtl_lpw/alut/rtl/alut_age_checker.v
./designs/socv/rtl/rtl_lpw/alut/rtl/alut_defines.v
./designs/socv/rtl/rtl_lpw/alut/rtl/alut_mem.v
./designs/socv/rtl/rtl_lpw/alut/rtl/alut_reg_bank.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subs.filelist
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.f
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem.irunargs
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/gpio_veneer.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/power_ctrl_veneer.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/smc_veneer.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/spi_veneer.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/ttc_veneer.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/uart0_veneer.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/uart1_veneer.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/alut_veneer.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem_0.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/rtl/apb_subsystem_1.v
./designs/socv/rtl/rtl_lpw/apb_subsystem/topologies/
./designs/socv/rtl/rtl_lpw/apb_subsystem/topologies/all_apb_black_boxed.topology
./designs/socv/rtl/rtl_lpw/apb_subsystem/topologies/uart0_not_black_boxed.topology
./designs/socv/rtl/rtl_lpw/apb_subsystem/topologies/uart0_uart1_not_black_boxed.topology
./designs/socv/rtl/rtl_lpw/apb_subsystem/topologies/uart1_not_black_boxed.topology
./designs/socv/rtl/rtl_lpw/apb_subsystem/topologies/uart_not_black_boxed.topology
./designs/socv/rtl/rtl_lpw/cdn_busmatrix/
./designs/socv/rtl/rtl_lpw/cdn_busmatrix/arbiter.v
./designs/socv/rtl/rtl_lpw/cdn_busmatrix/bm_defs.v
./designs/socv/rtl/rtl_lpw/cdn_busmatrix/bm_params.v
./designs/socv/rtl/rtl_lpw/cdn_busmatrix/busmatrix.irunargs
./designs/socv/rtl/rtl_lpw/cdn_busmatrix/busmatrix.v
./designs/socv/rtl/rtl_lpw/cdn_busmatrix/master_if.v
./designs/socv/rtl/rtl_lpw/cdn_busmatrix/multiplexer.v
./designs/socv/rtl/rtl_lpw/cdn_busmatrix/req_register.v
./designs/socv/rtl/rtl_lpw/cdn_busmatrix/slave_if.v
./designs/socv/rtl/rtl_lpw/cdn_chip/
./designs/socv/rtl/rtl_lpw/cdn_chip/rtl/
./designs/socv/rtl/rtl_lpw/cdn_chip/rtl/ahb2ocp.v
./designs/socv/rtl/rtl_lpw/cdn_chip/rtl/ahb2ocp_defs.v
./designs/socv/rtl/rtl_lpw/cdn_chip/rtl/ahb2ocp_ram.v
./designs/socv/rtl/rtl_lpw/cdn_chip/rtl/ocp_rtl.conf
./designs/socv/rtl/rtl_lpw/cdn_chip/topologies/
./designs/socv/rtl/rtl_lpw/cdn_chip/topologies/ahb_bus_only.topology
./designs/socv/rtl/rtl_lpw/cdn_chip/topologies/apb_and_mipi_black_boxed.topology
./designs/socv/rtl/rtl_lpw/cdn_chip/topologies/mipi_only.topology
./designs/socv/rtl/rtl_lpw/cdn_chip/topologies/ocp_and_mipi_black_boxed.topology
./designs/socv/rtl/rtl_lpw/dma/
./designs/socv/rtl/rtl_lpw/dma/rtl/
./designs/socv/rtl/rtl_lpw/dma/rtl/dma.f
./designs/socv/rtl/rtl_lpw/dma/rtl/dma.irunargs
./designs/socv/rtl/rtl_lpw/dma/rtl/dma.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_ahb_config.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_ahb_master.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_ahb_mux.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_apb_mux.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_arbiter.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_channel.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_defs.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_flow_mux.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_int_control.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_rx_sm.v
./designs/socv/rtl/rtl_lpw/dma/rtl/dma_tx_sm.v
./designs/socv/rtl/rtl_lpw/gpio/
./designs/socv/rtl/rtl_lpw/gpio/rtl/
./designs/socv/rtl/rtl_lpw/gpio/rtl/gpio_lite.f
./designs/socv/rtl/rtl_lpw/gpio/rtl/gpio_lite.irunargs
./designs/socv/rtl/rtl_lpw/gpio/rtl/gpio_lite.v
./designs/socv/rtl/rtl_lpw/gpio/rtl/gpio_lite_subunit.v
./designs/socv/rtl/rtl_lpw/mem_wrap/
./designs/socv/rtl/rtl_lpw/mem_wrap/rtl/
./designs/socv/rtl/rtl_lpw/mem_wrap/rtl/ROM_SP_512x32_wrap.v
./designs/socv/rtl/rtl_lpw/mem_wrap/rtl/SRAM_DP_512x36_wrap.v
./designs/socv/rtl/rtl_lpw/mem_wrap/rtl/SRAM_DP_64x36_wrap.v
./designs/socv/rtl/rtl_lpw/mem_wrap/rtl/SRAM_SP_16x128_wrap.v
./designs/socv/rtl/rtl_lpw/mem_wrap/rtl/SRAM_SP_2kx32_wrap.v
./designs/socv/rtl/rtl_lpw/mem_wrap/rtl/SRAM_SP_4kx32_wrap.v
./designs/socv/rtl/rtl_lpw/mem_wrap/rtl/SRAM_SP_512x8_wrap.v
./designs/socv/rtl/rtl_lpw/mem_wrap/rtl/SRAM_SP_8kx32_wrap.v
./designs/socv