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EX5/db/VGA_8_VERILOG.qns
EX5/db/VGA_8_VERILOG.root_partition.map.reg_db.cdb
EX5/db/VGA_8_VERILOG.routing.rdb
EX5/db/VGA_8_VERILOG.rtlv.hdb
EX5/db/VGA_8_VERILOG.rtlv_sg.cdb
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EX5/db/VGA_8_VERILOG.sas
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EX5/db/VGA_8_VERILOG.sgdiff.hdb
EX5/db/VGA_8_VERILOG.sld_design_entry.sci
EX5/db/VGA_8_VERILOG.sld_design_entry_dsc.sci
EX5/db/VGA_8_VERILOG.smart_action.txt
EX5/db/VGA_8_VERILOG.sta.qmsg
EX5/db/VGA_8_VERILOG.sta.rdb
EX5/db/VGA_8_VERILOG.sta_cmp.5_slow.tdb
EX5/db/VGA_8_VERILOG.syn_hier_info
EX5/db/VGA_8_VERILOG.taw.rdb
EX5/db/VGA_8_VERILOG.tis_db_list.ddb
EX5/db/VGA_8_VERILOG.vpr.ammdb
EX5/incremental_db/compiled_partitions/VGA_8_VERILOG.db_info
EX5/incremental_db/compiled_partitions/VGA_8_VERILOG.root_partition.map.kpt
EX5/incremental_db/README
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EX5/output_files/VGA_8_VERILOG.done
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EX5/output_files/VGA_8_VERILOG.fit.rpt
EX5/output_files/VGA_8_VERILOG.fit.smsg
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EX5/simulation/modelsim/VGA_8_VERILOG_run_msim_rtl_verilog.do
EX5/simulation/modelsim/VGA_8_VERILOG_v.sdo
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EX5/simulation/modelsim/rtl_work/@v@g@a_8_@v@e@r@i@l@o@g
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EX5/output_files
EX5/simulation
EX5